1. Instructor: Prof. Levitan, Prof. Jones Student: Xinyu Yi
ECE 1193 VLSI
Individual Presentation
Instructor: Prof. Levitan, Prof. Jones
Student: Xinyu Yi

2. Parallel to Series Component
Teams I joined
Parallel to Series Component
(Single Clock) 1
Switch
Design and Comparison 2
Bit Converter
(Double Clocks) 3
System Level Integration 4

3. Parallel to Series Component (Single Clock)
Parallel signal bus
P2S
Single bit series signal
Clock
What I did:
Basic Synopsys Design Compiler (DC)
Export and Analysis Timing report.
Use Encounter to generate layout.
Conclusion:
Get familiar with the Compiler and Encounter tools.

4. Switch Design and Comparison
What I did:
Design the MUX and DEMUX switch using VHDL code.
Estimate Area and timing by compile and place and route
Conclusion:
MUX and DEMUX are not the best choice for Switch.

5. Bit Converter (Double Clocks)
Parallel signal bus
Parallel signal bus
P2S
Single bit series signal
S2P
Clock(slow)
Clock(fast)
What I did:
Edit the TCL script ( Double Clocks implement and Setting Timing Constraints) and .do. ( Some Variables and Math)
Read Encounter menu and perform timing closure.
Import and Export files between Virtuoso, Encounter and Abstract.
Conclusion:
Now the Bit converter and run at 80Mhz/800Mhz. Final Netlist, Layout block are ready.

6. System Level Integration
What I did:
Flow the same procedure of Bit converter to analysis and design the Router ( With P2S, S2P, Buffers)
Conclusion:
Get the layout of this basic router but some components are not ready yet.

7. Thanks!