1. Track Trigger Meeting 1/17/2013
Status: SOWs for universities are still in process – let me know of urgent needs. Last news on “back up” lot of 18 wafers was mid December 4 pairs were being bonded at EVG in Austria. An additional 4 pairs will be bonded at Ziptronix Tezzaron has bought the Austin SVTC fab – renamed Novati this gives them on-shore fabrication facilities. The turn-around should be much much better (it can’t be worse)

2. Active Edge
Delayed the meeting at Ziptronix until top wafers are available from Cornell. CNF is having trouble fabricating the tungsten damascene wafers
Could use copper but there are issues with using copper in ion etch machines
Walter has done an initial set of measurements
Wafer is now at Brown for further tests
Discussions today at SLAC with Chris Kenney on processing

3. MPA: overall block diagram
to SSA
MPixel Event
Store FE
from MPixel column
Event Formatter
Strip Event
Store
CLK Generation & Cntrl
@ L1
Clocks
MPA Architecture - M.A.
Position decoder
Config Regs
Windowed pT coincidence
Strip
Intf to GBT
Link
Wide cluster elimination
Trigger Logic
@ each BX

4. Collaboration on ROIC
We have received a writeup of the current version of the CERN design from Sandro Maccioro and have forwarded some questions. We hope to have a phone meeting to go over these issues next week. In the interim we will proceed with the micropipeline layout. We also have to decide whether we want to work on a via-last test with CERN wafers or use our own design which could approximate the interconnections in a module.

5. Bump bonding
The initial attempt to bump bond sensors to the VICTR failed (the assembly fell apart in shipment). Two other VICTR chips are in Davis, one with solder ball and the other with gold studs. The gold studded assembly does not have clearance for the wirebonds. A thicker (1mm) PC board interposer arrived on Wednesday which should allow the bonding (next week?).

6. Via Last
Have quotation from allvia for processing CERN wafers. Need to obtain an NDA from Novati for their process Sandro: “For the wafers for AllVia we can provide you most likely with 2+2 wafers rather soon. With this I mean two wafers without IBM C4 bumps to be used as wafers to drill TSVs by AllVia and 2 wafers with IBM C4 bumps imitating a detector on top of the other chip. In fact, initially to test their TSVs you can work with a single type of chip. ”

7. a

8. Non-Interposer Module Drawings