1. Clock & Control Card Status 29 July 2008 Martin Postranecky/Matt Warren
ABSTRACT:
A data acquisition system is described which will be used for the next generation of prototype calorimeters for the International Linear Collider and could also be used for the final system. The design is sufficiently generic such that it should have applications elsewhere, be they other ILC detectors or within High Energy Physics in general: e.g. this could be applied to LHC upgrade apparatus. The concept of moving towards a "backplaneless" readout is pursued. A strong under-pinning thread here is to attempt to make use of commercial components and identify any problems with this approach. Therefore the system should be easily upgradable, both in terms of ease of acquiring new components and competitive prices. The conceptual design, both hardware and software, of the data acquisition system for the ILC calorimeter will be discussed. Results and tests already done will then be shown indicating both the potential and limitations of the approach.

2. C&C Logic and Interfaces (UPDATE)
CPLD (XCR3128XL-7) replacing many jumpers and switch logic
RS232 interface as a means of control
Many buffers, 0Ω resistors and solder links for better signal integrity, isolation and configuration
Signal Inputs:
CLOCK
1x LVDS (SMA DC)
1x LVTTL DC (Lemo)
1x NIM/TTL (Lemo) AC/DC
ASYNC
LVDS (SMA) DC
ECL (2 pin LEMO) AC
Controls (SYNCCMD, BUSY etc. + more)
4x LVDS (SMA)
4x NIM/TTL (Lemo) AC/DC
Signal Outputs:
CLOCK
2x LVTTL on Lemo
2x NIM on Lemo
2x LVDS on SMA
8x LVDS on DIL Header
TRAINSYNC
LVTTL on Lemo
GEN (was Busy)
LVDS on SMA
NIM on Lemo
OC-TTL on Lemo
Spare (DATA_D2L)
HDMI I/O: x8
- LVDS AC/DC
OUT:
CLOCK
ASYNC
TRAINSYNC
IN:
GEN (was BUSY)
SPARE(DATA_D2L)
*NO RJ45
29 July 08
Martin Postranecky/Matt Warren - C&C Status

3. Martin Postranecky/Matt Warren - C&C Status
Overview Schematic
NOTES:
CPLD + Gates
Busy == Gen
Added SPARE line
Delayed clock option
4x 8 way DIL to CPLD
CLOCK
AUTO/ XTAL SW
LVDS on SMA
LVTTL on Lemo
8x LVDS on HDMI
NIM/TTL on Lemo
MPX +PLL
8x LVDS on SMA
2x LVTTL on Lemo
~50 MHz
2x NIM on Lemo
X-TAL
ASYNC
clock
LVDS on SMA SW
8x LVDS on HDMI
ECL on 2pin Lemo
DELAY
Controls (SYNCCMD, BUSY-IN etc)
4x LVDS on SMA
4x NIM on Lemo 4x 4
SW-2 5->1 4
8x LVDS on HDMI
GEN (was BUSY)
LVDS on SMA
CPLD
(Xilinx
Coolrunner
XCR3128XL-7)
SW-3 2->1
NIM on Lemo
8x LVDS on HDMI
o/c TTL on Lemo 4
SPARE (DATA_D2L)
8x LVDS on HDMI
LVTTL on Lemo
RS232
DEBUG 4x 8way DIL
PCB Header
29 July 08
Martin Postranecky/Matt Warren - C&C Status

4. Martin Postranecky/Matt Warren - C&C Status
Some Hardware Details
Clock:
PLL/MUX - ICS581-02
+/-150 ps jitter
45min/55max Duty Cycle
Failover if external clock missing for 3 cycles.
Local Osc. 100 MHz/2 = 50% duty-cycle 50MHz
CPLD: Xilinx CoolRunner XPLA3 XCR3128XL-7
3.3V, low power
128 macrocells with 3,000 usable gates
5.5ns pin-to-pin logic delays
Extra IO via IDC header.
Single PCB with connectors at the edge (big!)
Separate PSU
Clock Delay Option to CPLD – 64x0.5ns?
For signal deskew (CLOCK unaffected)
29 July 08
Martin Postranecky/Matt Warren - C&C Status

5. Martin Postranecky/Matt Warren - C&C Status
Rough Board Layout
Notes:
Eurocard size (234x220mm)
SMAs Vertical
29 July 08
Martin Postranecky/Matt Warren - C&C Status

6. Martin Postranecky/Matt Warren - C&C Status
Status/Schedule UPDATE
Schematic DONE.
Double checked
But getting mods (delay)
Layout
Initial: in-progress, may be done now.
Final: mid-Aug (was mid-June)
Manufacture
Mid-Sept (was July/Aug)
29 July 08
Martin Postranecky/Matt Warren - C&C Status