1. The University of Adelaide, School of Computer Science
14 September 2018
Chapter 2
Instructions: Language of the Computer
Chapter 2 — Instructions: Language of the Computer

2. The University of Adelaide, School of Computer Science
14 September 2018
Register Operands
Arithmetic instructions use register operands
LEGv8 has a 32 × 64-bit register file
Use for frequently accessed data
64-bit data is called a “doubleword”
31 x 64-bit general purpose registers X0 to X30
32-bit data called a “word”
31 x 32-bit general purpose sub-registers W0 to W30
Why only 32 registers?
Design Principle 2: Smaller is faster
the number of bits it would take in the instruction format
c.f. main memory: millions of locations
§2.3 Operands of the Computer Hardware
Chapter 2 — Instructions: Language of the Computer

3. LEGv8 Registers X0 – X7: procedure arguments/results
X8: indirect result location register
X9 – X15: temporaries
X16 – X17 (IP0 – IP1): may be used by linker as a scratch register, other times as temporary register
X18: platform register for platform independent code; otherwise a temporary register
X19 – X27: saved
X28 (SP): stack pointer
X29 (FP): frame pointer
X30 (LR): link register (return address)
XZR (register 31): the constant value 0

4. Register Operand Example
The University of Adelaide, School of Computer Science
14 September 2018
Register Operand Example
Compiling a C Assignment Using Registers:
f = (g + h) - (i + j);
f, g, h, i, j in X19, X20, X21, X22, X23
Compiled LEGv8 code:
ADD X9, X20, X21 // register X9 contains g + h ADD X10, X22, X23 // register X10 contains i + j SUB X19, X9, X10 // f gets X9−X10, which is (g + h)−(i + j)
Chapter 2 — Instructions: Language of the Computer

5. The University of Adelaide, School of Computer Science
14 September 2018
Memory Operands
Main memory used for composite data
Arrays, structures, dynamic data
Data transfer instructions: transfer data between memory and registers (load and store)
To access a word or doubleword in memory, the instruction must supply the memory address, usually starting at 0.
Chapter 2 — Instructions: Language of the Computer

6. Memory Operands LDUR – load register, U for unscaled immediate
To apply arithmetic operations
Load values from memory into registers
Store result from register to memory
Memory is byte addressed
Each address identifies an 8-bit byte
LEGv8 does not require words to be aligned in memory, except for instructions and the stack
LDUR – load register, U for unscaled immediate
STUR – store register

7. Memory Operand Example
The University of Adelaide, School of Computer Science
14 September 2018
Memory Operand Example
Compiling Using Load and Store:
A[12] = h + A[8];
h in X21, base address of A in X22
Compiled LEGv8 code:
Index 8 requires offset of 64 (8x8)
Index 12 requires offset of 96 (8x12)
LDUR X9,[X22,#64] // Temporary reg X9 gets A[8]
ADD X9,X21,X9 // Temporary reg X9 gets h + A[8]
STUR X9,[X22,#96] //Stores h + A[8] back into A[12]
Chapter 2 — Instructions: Language of the Computer

8. The University of Adelaide, School of Computer Science
14 September 2018
Registers vs. Memory
Registers are faster to access and have higher throughput than memory
also uses much less energy than accessing memory
Operating on memory data requires loads and stores
More instructions to be executed
Compiler must use registers for variables as much as possible
Only spill to memory for less frequently used variables, called spilling registers
Register optimization is important!
Assuming 64-bit data, registers are roughly 200 times faster (0.25 vs. 50 nanoseconds) and are 10,000 times more energy efficient (0.1 vs picoJoules) than DRAM in 2015.
Chapter 2 — Instructions: Language of the Computer

9. Constant or Immediate Operands
The University of Adelaide, School of Computer Science
14 September 2018
Constant or Immediate Operands
Constant data specified in an instruction
ADDI X22, X22, #4 // X22 = X22 + 4
ADDI - add immediate
Design Principle 3: Make the common case fast
Small constants are common
Immediate operand avoids a load instruction
LEGv8 dedicates a register XZR to be hard-wired to the value zero (register number 31)
Chapter 2 — Instructions: Language of the Computer

10. Unsigned Binary Integers
The University of Adelaide, School of Computer Science
14 September 2018
Unsigned Binary Integers
Given an n-bit number
§2.4 Signed and Unsigned Numbers
Range: 0 to +2n – 1
Example
= 0 + … + 1×23 + 0×22 +1×21 +1×20 = 0 + … = 1110
Using 32 bits
0 to +4,294,967,295
Chapter 2 — Instructions: Language of the Computer

11. 2s-Complement Signed Integers
The University of Adelaide, School of Computer Science
14 September 2018
2s-Complement Signed Integers
Given an n-bit number
Range: –2n – 1 to +2n – 1 – 1
Example
= –1× ×230 + … + 1×22 +0×21 +0×20 = –2,147,483, ,147,483,644 = –410
Using 32 bits
–2,147,483,648 to +2,147,483,647
Chapter 2 — Instructions: Language of the Computer

12. 2s-Complement Signed Integers
The University of Adelaide, School of Computer Science
14 September 2018
2s-Complement Signed Integers
Bit 31 is sign bit
1 for negative numbers
0 for non-negative numbers
–(–2n – 1) can’t be represented
Non-negative numbers have the same unsigned and 2s-complement representation
Some specific numbers
0: … 0000
–1: … 1111
Most-negative: … 0000
Most-positive: … 1111
Chapter 2 — Instructions: Language of the Computer

13. The University of Adelaide, School of Computer Science
14 September 2018
Signed Negation
Complement and add 1
Complement means 1 → 0, 0 → 1
Example: negate +2
+2 = … 0010two
–2 = … 1101two = … 1110two
Chapter 2 — Instructions: Language of the Computer

14. The University of Adelaide, School of Computer Science
14 September 2018
Sign Extension
Representing a number using more bits
Preserve the numeric value
Replicate the sign bit to the left
c.f. unsigned values: extend with 0s
Examples: 8-bit to 16-bit
+2: =>
–2: =>
In LEGv8 instruction set
LDURSB: sign-extend loaded byte
LDURB: zero-extend loaded byte
Chapter 2 — Instructions: Language of the Computer

15. Representing Instructions
The University of Adelaide, School of Computer Science
14 September 2018
Representing Instructions
Instructions are encoded in binary
Called machine code
LEGv8 instructions
Encoded as 32-bit instruction words
Small number of formats encoding operation code (opcode), register numbers, …
Simplicity favors regularity!
§2.5 Representing Instructions in the Computer 15
Chapter 2 — Instructions: Language of the Computer

16. The University of Adelaide, School of Computer Science
14 September 2018
Hexadecimal
Base 16
Compact representation of bit strings
4 bits per hex digit
0000 4
0100 8
1000 c
1100 1
0001 5
0101 9
1001 d
1101 2
0010 6
0110 a
1010 e
1110 3
0011 7
0111 b
1011 f
1111
Example: eca8 6420 16
Chapter 2 — Instructions: Language of the Computer

17. LEGv8 R-format Instructions
The University of Adelaide, School of Computer Science
14 September 2018
LEGv8 R-format Instructions
opcode Rm
shamt Rn Rd
11 bits
5 bits
6 bits
Instruction fields
opcode: operation code
Rm: the second register source operand
shamt: shift amount (00000 for now)
Rn: the first register source operand
Rd: the register destination 17
Chapter 2 — Instructions: Language of the Computer

18. The University of Adelaide, School of Computer Science
14 September 2018
R-format Example
opcode Rm
shamt Rn Rd
11 bits
5 bits
6 bits
ADD X9,X20,X21
1112ten
21ten
0ten
20ten
9ten
two
10101two
000000two
10100two
01001two
two = 8B 18
Chapter 2 — Instructions: Language of the Computer

19. LEGv8 D-format Instructions
The University of Adelaide, School of Computer Science
14 September 2018
LEGv8 D-format Instructions
opcode
op2 Rn Rt
11 bits
9 bits
2 bits
5 bits
address
Load/store instructions
Rn: base register
address: constant offset from contents of base register (+/- 32 doublewords)
Rt: destination (load) or source (store) register number
Design Principle 3: Good design demands good compromises
Different formats complicate decoding, but allow 32-bit instructions uniformly
Keep formats as similar as possible 19
Chapter 2 — Instructions: Language of the Computer

20. LEGv8 I-format Instructions
The University of Adelaide, School of Computer Science
14 September 2018
LEGv8 I-format Instructions
opcode Rn Rd
10 bits
12 bits
5 bits
immediate
Immediate instructions, e.g. ADDI, SUBI
Rn: source register
Rd: destination register
Immediate field is zero-extended
Reduce the complexity by keeping the formats similar
Figure 2.5 LEGv8 instruction encoding.
In the table above, “reg” means a register number between 0 and 31, “address” means a 9-bit address or 12-bit constant, and “n.a.” (not applicable) means this field does not appear in this format. The op2 field expands the opcode field. 20
Chapter 2 — Instructions: Language of the Computer

21. Example Translating LEGv8 Assembly Language into Machine Language
A[30] = h + A[30] + 1;
X10 has the base of the array A and X21 corresponds to h
Compiled LEGv8 code:
LDUR X9, [X10,#240] // Temporary reg X9 gets A[30]
ADD X9,X21,X9 // Temporary reg X9 gets h+A[30]
ADDI X9,X9,#1 // Temporary reg X9 gets h+A[30]+1
STUR X9, [X10,#240] // Stores h+A[30]+1 back into A[30]
Machine language instructions using decimal numbers:
opcode
Rm/
address
shamt/op2 Rn
Rd/Rt
1986
240 10 9 00
01010
01001
1112 21
000000
10101
580 1
1984 21

22. Summary of LEGv8 machine language (till this point)
Figure 2.6 LEGv8 architecture revealed through Section 2.5.
The three LEGv8 instruction formats so far are R, I and D. The last 10 bits contain a Rn field, giving one of the sources; and the Rd or Rt field, which specifies the destination register, except for store register, where it specifies the value to be stored. R-format divides the rest into an 11-bit opcode; a 5-bit Rm field, specifying the other source operand; and a 6-bit shamt field, which Section 2.6 explains. I-format combines 12 bits into a single immediate field, which requires shrinking the opcode field to 10 bits. The D-format uses a full 11-bit opcode like the R-format, plus a 9-bit address field, and a 2-bit op2 field. The op2 field is logically an extension of the opcode field. 22

23. Stored Program Computers
The University of Adelaide, School of Computer Science
14 September 2018
Stored Program Computers
Instructions represented in binary, just like data
Instructions and data stored in memory
Programs can operate on programs
e.g., compilers, linkers, …
Binary compatibility allows compiled programs to work on different computers
Standardized ISAs
The BIG Picture 23
Chapter 2 — Instructions: Language of the Computer

24. The University of Adelaide, School of Computer Science
14 September 2018
Logical Operations
Instructions for bitwise manipulation
§2.6 Logical Operations
Operation C
Java
LEGv8
Shift left
<<
LSL
Shift right
>>
>>>
LSR
Bit-by-bit AND
&
AND, ANDI
Bit-by-bit OR |
OR, ORI
Bit-by-bit NOT ~
EOR, EORI
Useful for extracting and inserting groups of bits in a word 24
Chapter 2 — Instructions: Language of the Computer