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Implementation of the Jet Algorithm ATLAS Level-1 Calorimeter Trigger
Anders Ferm Torbjörn Söderström
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Design goals Produce a jet algorithm able to accept and process new input data every 12.5 ns Reduce logic usage as much as possible Reduce latency as much as possible Avoid unnecessary calculations
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Data path TTC Config VME Control FPGA Main processor FPGA
5 bit elements to neighbours, 80Mb/s Config VME Control FPGA Jet count to merger, 40Mb/s 88 LVDS links from PPr Main processor FPGA Energy sums to merger, 40Mb/s 88 pairs at 400Mb/s 8*10 bit 40Mb/s 5 bit elem, 80Mb/s 88 de-serialisers 11 Input FPGA:s ROC FPGA DAQ G-link ROI G-link 5 bit elements from neighbours, 80Mb/s
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+ 1 Create cluster sums 2 Identify local maxima
32 2x2 45 3x3 32 4x4 3 Try the clusters against the thresholds 4 Count Jets Regions of interest + Numbers of passed thresholds 1 1 1 1 1
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Adding schematic – version 1
Input 77 Jet elements (2X5 bits Least Significant First) Step 1 Step 2 Step 3 Step 4 Compare 2X2 neighbours 2X2 2X2 4X4 1X2 2X2 2X4 3X3 2X3 1X3 40 Mhz
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Adding schematic – final version
Input 77 Jet elements (2X5 bits Least Significant First) Step 1 Step 2 Step 3 Compare 2X2 neighbours. 2X2 4X4 2X2 2X2 2X4 1X2 3X3 3X3 2X3 1X3 40 Mhz
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Eliminating redundant summations
10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 Sums sharing the same 12 cluster 1 2 3 4 5 6 1 2 3 4 5 6
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Local maxima Compare 2x2 neighbours
<
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Comparators can be shared
A B B > A B > A A B <
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Jet algorithm block scheme
8 threshold comparators 2x2 2x2 Threshold comparators Pipeline 1x1 OF 8x8 Jet counters Adder tree 2x2 Identify local maxima Max OF Count Jets 1x1 2x2 4x4 Pipeline Adder tree 4x4 Numbers of passed thresholds 1x2 OF OF OF OF 1x3 3x3 3x3 1x1 Adder tree 1x3 Adder tree 3x3 Pipeline Passed thresholds signals OF OF OF OF Thresholds Size
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Section of adder tree (1x3 and 2x2 cluster sums)
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Identifying maxima by 2x2 comparators
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Region of Interest (RoI)
Outputs Region of Interest (RoI) 10 RoI location 9 8 ROI 3 ROI 7 01 11 00 10 7 6 ROI 2 ROI 6 5 4 ROI 1 ROI 5 Jet algorithm outputs 3 2 ROI 0 ROI 4 Parity ROI location Saturate flag Thresholds passed 11 10 9 8 7 1 1 2 3 4 5 6
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Maxima identification
Good design vs Bad design 160 comparators instead of 256
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Creating 2x2 cluster sums
Good design vs Bad design 95 additions instead of 135
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Two ways to make threshold definition component x8
Compare 3x3 1 3x3 Size select x8 (6 comparators) 6 + 8 = 14 comparators 8x4 = 32 comparators
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Xilinx v1500bg575-4 Device utilization
Resource Used Available Utilization Function generators 5 406 15 360 35.20% CLB slices 2 703 7 680 35.20% Dffs or latches 4 173 16 536 25.02% Clock frequency Clock Frequency Clk80MHz 98.4 MHz
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The VHDL code together with a C++ test code are available at:
World Wide Web link The VHDL code together with a C++ test code are available at:
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