1. I2C PROTOCOL SPECIFICATION
A SEMINAR ON
I2C PROTOCOL SPECIFICATION
PRESENTED BY:
SANKULA SIVA SANKAR
S.S.G.KRIHNA YADAV .K
KANCHI SRILATHA
V.VAMSI KRISHNA
M.NIKLESH REDDY
Under guidance of
PADMANABAM

2. Copyright CoreEL Technologies (I) Pvt. Ltd.
What is I2C
The name stands for “Inter - Integrated Circuit Bus”
A Small Area Network connecting ICs and other electronic systems
Originally intended for operation on one single board / PCB
Synchronous Serial Signal
Two wires carry information between a number of devices
One wire use for the data
One wire used for the clock
Today, a variety of devices are available with I2C Interfaces
Microcontroller, EEPROM, Real-Timer, interface chips, LCD driver, A/D converter
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

3. Copyright CoreEL Technologies (I) Pvt. Ltd.
Why I2C ?
Data transfer between ICs and systems at relatively low rates
“Classic” I2C is rated to 100K bits/second
“Fast Mode” devices support up to 400K bits/second
A “High Speed Mode” is defined for operation up to 3.4M bits/second
Reduces Board Space and Cost By:
Allowing use of ICs with fewer pins and smaller packages
Greatly reducing interconnect complexity
Allowing digitally controlled components to be located close to their point of use.
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

4. I2C Bus Characteristics
Includes electrical and timing specifications, and an associated bus protocol
Two wire serial data & control bus implemented with the serial data (SDA) and clock (SCL) lines
Unique start and stop condition
Slave selection protocol uses a 7-Bit slave address
The bus specification allows an extension to 10 bits
Bi-directional data transfer
Acknowledgement after each transferred byte
No fixed length of transfer
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

5. Copyright CoreEL Technologies (I) Pvt. Ltd.
Features
Low current consumption
High noise immunity
Wide supply voltage
Wide operating temperature range
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

6. Copyright CoreEL Technologies (I) Pvt. Ltd.
I2C specification
Single master single slave
I2C synchronizer
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

7. Copyright CoreEL Technologies (I) Pvt. Ltd.
Top level diagram
Hireachy :
CLOCK
RESET
SCL
I2C MASTER
CONTROLLER
ADDRESS
MICRO PROCESSOR
I2C slave
SDA
DATA
R/W
INTR
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

8. i_reset
SCK_o
i_clk
SDA_i
i_slave_address_reg
SDA_o
i_config_reg
o_start_ack
Micro
processor
I2C MASTER
o_cmd_status_reg
i_transmit_data
o_tansmit_data_request
o_receive_data request
o_receive _data

9. Priorities
1.Asynchronous reset(i_reset_n). 2.Start acknowledgement(o_start_ack) 3.Transmit Interrupt enable(TX_IE),Receive Interrupt enable(RX_IE) 4.Transmit data request(o_tansmit_data_request), 5.TX_DONE. 6.Receive_data _request(o-receive_data_request), 7.RX_DONE.

10. Copyright CoreEL Technologies (I) Pvt. Ltd.
I2C master
Processor to master
CLOCK
RESET
I2C MASTER
CONTROLLER
ADDRESS
MICRO PROCESSOR
DATA
R/W
INTR
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

11. Copyright CoreEL Technologies (I) Pvt. Ltd.
I2C SLAVE
reset
SCL
Memory element
SCL
SDA
I2C slave
SDA
I2C master
INT
R/w
address
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

12. Copyright CoreEL Technologies (I) Pvt. Ltd.
I2C Bus Definitions
Master:
Initiates a transfer by generating start and stop conditions
Generates the clock
Transmits the slave address
Determines data transfer direction
Slave:
Responds only when addressed
Timing is controlled by the clock line
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

13. Copyright CoreEL Technologies (I) Pvt. Ltd.
Pin Description
SIGNAL NAME
SIGNAL DIRECTION
DEFINITION
ACTIVE STATE
Clock
Input
Microprocessor clock
N/A
Reset
System reset
Active Low
Address
Address bits reading and writing to configuration and data registers
Data
Bi-directional
Data bus RW
1 = RD
0 = WR
INTR
Output
SDA
I2C Data bus line
SCL
Uni-directional
I2C Clock line
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

14. Copyright CoreEL Technologies (I) Pvt. Ltd.
DATA TRANSFER:
Every byte on the SDA line must be 8-bits long. The number of bytes that can be transmitted per transfer is unrestricted.
Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit (MSB) first.
Master sends start condition (S) and controls the clock signal
Master sends a unique 7-bit slave device address
Master sends read/write bit (R/W) – 0 - slave receive, 1 - slave transmit
Slave with matching 7-bit device address always sends acknowledge bit (ACK)
Transmitter (slave or master) transmits 1 byte of data
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

15. Copyright CoreEL Technologies (I) Pvt. Ltd.
I2C Bus Transfer
Multiple bytes sent in a transaction; every 8 bits has a 9th bit that is an acknowledge.
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

16. Copyright CoreEL Technologies (I) Pvt. Ltd.
Write (master to slave)
Master initiates all transactions, read or write.
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

17. Bit Transfer on the I2C Bus
In normal data transfer, the data line only changes state when the clock is low
SDA
SCL
Data line stable; Data valid
Change of data allowed
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

18. Start and Stop Conditions
A transition of the data line while the clock line is high is defined as either a start or a stop condition.
Both start and stop conditions are generated by the bus master
The bus is considered busy after a start condition, until a stop condition occurs
Start Condition
Stop Condition
SCL
SDA
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

19. First Byte in Data Transfer on the I2C Bus
MSB
ACK
LSB
7 – Bit Slave Address
R / Wr
R/Wr 0 – Slave written to by Master
1 – Slave read by Master
ACK – Generated by the slave whose address has been output.
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

20. Copyright CoreEL Technologies (I) Pvt. Ltd.
Acknowledgements
Master/slave receivers pull data line low for one clock pulse after reception of a byte
Master receiver leaves data line high after receipt of the last byte requested
Slave receiver leaves data line high on the byte following the last byte it can accept
Acknowledgement from receiver
Transmitter releases SDA line during 9th clock pulse.
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

21. Data Transfer on the I2C Bus
Start Condition
Slave address + R/W
Slave acknowledges with ACK
All data bytes
Each followed by ACK
Stop Condition
ACK from Slave
ACK from Receiver
Remember : Clock is produced by Master
Start
Stop
SCL
SDA
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

22. Copyright CoreEL Technologies (I) Pvt. Ltd.
Data Formats
Master writing to a Slave A A A
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.

23. Copyright CoreEL Technologies (I) Pvt. Ltd.
1/21/2015
Copyright CoreEL Technologies (I) Pvt. Ltd.