1. Why we use banked Instruction Cache
To enable multiple threads to fetch instructions concurrently, the instruction cache must be able to supply multiple cache lines in the same cycle
Multiporting the cache, but this would substantially increase the size of the cache, slow it down, and increase the power consumption
That’s why we go with banked cache, adding a bank access controller that schedule the access to the bank [1]

2. Interleaved Organization I
Low-order interleaving, low-order bits of the address are used to identify the modules, the high-order bits are word addresses
High-order interleaving, high-order bits are module addresses, while low-order bits are word addresses

3. Interleaved Organization II
High- and low-order interleaving can be combined to yield different interleaved organizations, the high-order bits are used to address banks and the low-order bits are used to address modules, why middle bits used to address words
If fault tolerance is an issue which can not be ignored, then tradeoffs do exist between the degree of interleaving and the number of banks used.[2]

4. Cache design for a multithreaded Processor
Using multithreading in a single processor systems introduces changes in the memory referencing pattern, which effects the locality of reference and thus reducing the effectiveness of the cache.
The miss rate reduces as the associativity or the block size increases
No much gain by using accociativity greater than the number of threads
Achieve balance between block size and memory bandwidth [3]

5. Skewed-associative cache
A two-way skewed-associative cache has the same hardware complexity as a two-way set-associative cache, yet exhibits the same hit ratio as a four-way set-associative cache

6. References
Paramjit Oberoi and Gurindar Sohi, “Out-of-Order Instruction Fetch using Multiple Sequencers”, The 2002 International Conference on Parallel Processing, Aug 18–21, 2002
Kai Huang, “Advanced Computer Architecture – Parallelism, Scalability, Programmability”, McGraw-Hill 1993
Dimitris Liopis and Sotris Milios, “Exploring the Cache Design Space in a Multithreaded Processor”, University of Patras, Greece 
Andre Seznec, “A case for two-way skewed-associative caches”, ISCA 1993