1. Hardware platforms - with notes from during the meeting 17 March 2016
J. J. John
with input from many colleagues

2. Agenda Meetings reminder
Summarise hardware platform discussions since last ABCN’ meeting
(iterated at CMOS Fortnightly meetings and with Matt by )
Go over first steps and divide up
Meetings reminder
Following the poll, these will be every Thursday at 7:30am Pacific / 10:30am Eastern / 14:30 UK / 15:30 Geneva / 22:30 China
Link to series of meetings:
Attendees : Wojtek Fedorko, Jaya John John, Weiguo Lu, Matt Warren
Apologies : Hervé Grabas, Paul Keener

3. ABCN’ hardware – phase 1
First platform will be Nexys Video = new ITk Strips/ITSDAQ platform
All functions within one FPGA => avoid dependence on any FMC-to-X adaptor boards (FMC = FPGA Mezzanine Connector, data connector on Nexys Video)
Nexys Video
SCTDAQ s/w with adaptations
FPGA
CHESS-2 Data Emulator
ABCN’
ITSDAQ control and readout
DAQ s/w
Ethernet
logical blocks within FPGA
We agreed this was the best starting point.

4. ABCN’ hardware – phase 2
After discussion: there is a good deal to learn about timing when we run the DAQ on separate hardware, so to avoid surprises, we should not skip this step.
Nexys Video
SCTDAQ s/w with adaptations
FPGA
Atlys
CHESS-2 Data Emulator
ABCN’
F2V adaptor board
DAQ h/w
DAQ s/w
FMC connector
VHDCI cable
Ethernet cable
logical blocks within FPGA
not so many available yet, also limited pin count => best to wait for updated FMC-to-X adaptor?
Nexys Video
FPGA
Nexys Video
CHESS-2 Data Emulator
ABCN’
F2V adaptor board
F2V adaptor board
DAQ h/w
VHDCI cable
FMC
Ethernet
logical blocks within FPGA
SCTDAQ s/w with adaptations
DAQ s/w

5. ABCN’ hardware – phase 3
First hardware with a CHESS-2 chip = CHESS-2 readout system by SLAC The ABCN’ code will be added as a block within an FPGA on the HSIO-2:
CHESS-2 board(s)
HSIO-2
CHESS-2
Array 1, 128 strips
Test structures
Array 2, 128 strips
Array 3, 128 strips
FPGA
Usual HSIO-2 firmware/contents
RCE s/w
ABCN’
DAQ s/w
power
logical blocks within FPGA
It will be some learning to be able to integrate the ABCN’ code onto an FPGA on the HSIO-2 and learn to operate the software.
the partitioning of the boards, and need for any adaptor boards, are to be seen
After discussion: it is very important for this interface to be a standard connector, such as an FMC. Ideally, this would be an HPC FMC where the pins are set up so that an LPC FMC would have access to 2 of the 3 of the CHESS-2 arrays.
Then we could do first tests with our existing Nexys Video set-up, for example, to get going sooner.

6. ABCN’ hardware – phase 4 (reminder) CHESS-2 Demonstrator Module
CHESS-2 2 x 2.4cm
CHESS-2 2 x 2.4cm
hybrid/PCB
hybrid/PCB
ABCN’
(FPGA)
power
Array 1, 128 strips
Test structures
Array 2, 128 strips
Array 3, 128 strips
Array 1, 128 strips
Test structures
Array 2, 128 strips
Array 3, 128 strips
ABCN’
(FPGA)
power
Array 1, 128 strips
Test structures
Array 2, 128 strips
Array 3, 128 strips
Array 1, 128 strips
Test structures
Array 2, 128 strips
Array 3, 128 strips
hybrid/PCB may extend as baseboard, to be seen