1. A Low-Noise and Low-Power LNA and Mixer for 24-GHz Application
Advanced Science and Technology Letters Vol.74 (ASEA 2014), pp.41-44
A Low-Noise and Low-Power LNA and Mixer for 24-GHz Application
Habib Rastegar, Cheol-Hwan Kim, Myeong-U Seong, Seung-Kyu Choi, Geun- Ho Choi, Shin-Gon Kim, Ki-Jung Han, Seung-Woo Choi, Abu Abdoulaye Tall,
Jee-Youl Ryu
1 Pukyong Nat’l University, Dept. of Information and Communications Engineering, Busan, South Korea
Abstract- This paper presents the design of a low-voltage and low-power front-end. It consists of a low noise amplifier (LNA) which integrates with mixer, and downconverts an 24-GHz RF input signal to an IF of 8-GHz. The first stage (LNA) uses complementary-push-pull configuration to save power consumption as well as to increase the trans-conductance and gain. A PMOS transistor is biased in the moderate inversion region functions as active load for LNA. It also converts the input voltage signal to current signal for the succeeding block which is a down-conversion mixer. The single-balanced mixer is accomplished to convert high frequency to intermediate frequency. The designed RF front-end uses the folded architecture to reduce the supply voltage and hence, power consumption. The whole circuit draws only 1.53 mA from 0.9-V power supply. The proposed circuit showed conversion gain of 12 dB and noise figure of 5.5 dB for -12dBm LO power.
Keywords: LNA, mixer, folded cascade, IIP3
1 Introduction
The rapidly growing demand for larger bandwidth motivates RF circuits to move toward higher frequencies. At frequencies above 20 GHz, GaAs-based HEMT and HBT processes have occupied most of the applications in the past. Recent works have shown that the rapid development of CMOS devices have potential for building RF circuits at frequencies above 20 GHz [1]. At high frequency (RF) front-end receiver, there are several blocks to receive and modulate signal and hence, send it to the back- end. LNA as the first stage in receiver plays a vital role in any wireless receiver since the design involves many tradeoffs between noise figure (NF), gain and input impedance matching. Generally, the main goal of LNA is to achieve simultaneous high gain and low noise figure at a good input return loss. Mixer functions as the second block in the receiver chain to translate high frequency to IF one. Power consumption, conversion gain, linearity and silicon area are the main challenges of mixer. Gilbert cell is the most common topology for mixers. By increasing the bias current of the RF stage of the mixer, a reduction in noise figure and enhancement in
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2. Advanced Science and Technology Letters Vol.74 (ASEA 2014)
the linearity, increment in the conversion gain, will be also achieved. Explicitly, this method arises a tradeoff between power consumption and other performances. A popular technique to overcome the above-mentioned tradeoffs is folding structure. There are a number of works that have utilized this topology without sacrificing power consumption and achieve good gain and bandwidth [2, 3].
In this paper we propose a new combination of LNA and mixer topology based on the folded architecture. To improve linearity, LO stage is also realized using p-type MOSFETs and we will explain why this result in better linearity. Moreover, the LNA stage utilize complementary-push-pull configuration in order to boost the trans-conductance and to relax biasing constraint which results in better noise performance. Finally the mixer employs single-balanced Gilbert cell to downconvert high frequency to IF frequency.
2 LNA and Mixer Design
Fig. 1 illustrates the schematic of the proposed LNA and mixer. As can be seen, a folded architecture which consists of an inverter function as LNA and PMOS Gilbert cell as mixer. In the proposed circuit, LNA utilizes inverter topology which consists of PMOS and NMOS transistors stacked on top of each other to save power consumption and to increase gain and linearity. For inverter the total trans- conductance can be written as:
, = + (1) 1+
where gmn and gmp represent the tran-conductance of the NMOS and PMOS transistors, respectively.
For Gilbert cell, the conversion gain (CG) can be expressed as follows:
CG ∝ and ∝ , (2)
where RL is the load resistor of the mixer and IDC,LNA is LNA bias current.
Also, the third-order input intercept pint can be defined as follows:
IIP3= √3 ~,4
(3)
where KLNA=µ0C0x (W/L) is a process dependent parameter.
According to the above-mentioned formulas, the easiest way to achieve high gain and good linearity is to boost DC bias current. However, bias current is limited to the power budget and cannot increase to above value. Despite the fact, increment in bias current leads to increase the linearity of the LNA stage as well as the voltage drop on the load resistor increases. This voltage drop confines the LO switch voltage swing and hence, deteriorate the mixer linearity and reduce the linearity of whole circuit. Considering the noise figure, it makes the tradeoffs among noise figure, linearity and conversion gain so complicated.
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3. Fig. 1. Circuit schematic of the LNA and mixer.
Advanced Science and Technology Letters
Vol.74 (ASEA 2014)
As a conclusion based upon the above explanation, in this paper a folded CPP cascade structure has been chosen. With the proposed circuit, an inverter structure is chosen as LNA because of high linearity and gain. Based upon Eq. (1), the gain of LNA will be increased, because the trans-conductance of PMOS and NMOS transistors can be added up. Moreover, since in inverter topology the third-order trans-conductance (gm3) of PMOS and NMOS transistors cancelled out each other, high linearity can be achieved. While the mixer stage bias current is reduced to optimize it for low noise, low power consumption and high linearity because of minimization the load resistor drop voltage of mixer. The current of mixer can be written as follows:
'mixer = 'NMOS − 'PMOS (4)
where Imixer is the bias current of mixer, INMOS is the bias current of NMOS and IPMOS is the bias current of PMOS.
According to Eq. (4), the mixer bias current is very low because PMOS and NMOS are biased in moderate and strong inversion regions, respectively and hence has close current. Furthermore, the mixer is connected to LNA without any decoupling capacitor and therefore, it does not have any independent voltage supply. In conclusion, the whole circuit has only one voltage supply and has low power consumption. Also in this we propose to use PMOS for switches. Having PMOS switches in LO stage, helps to achieve same overdrive voltage, and consequently similar linearity performance with lower power consumption compared to the case using NMOS transistors [4].
Fig. 1. Circuit schematic of the LNA and mixer.
3 Simulation Results
The proposed LNA and mixer are simulated with 130nm CMOS RF process. Fig. 2 presents the conversion gain and noise figure. Fig. 2 also depicts the simulated results of IIP3. The simulated IIP3 at frequency 24-GHz with 100MHz spacing is 3dBm. The designed circuit consumes 1.53-mW from a 0.9-V voltage supply.
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4. 4 Conclusion References
Advanced Science and Technology Letters Vol.74 (ASEA 2014)
Fig. 2. Conversion gain, noise figure and IIP3 of the proposed circuit.
4 Conclusion
A combination of LNA and mixer designed and simulated in 130nm CMOS technology. The inverter configuration utilized as LNA to achieve high gain and linearity. The switches in the mixer are designed in PMOS to enhance the linearity performance and power consumption. Moreover, the whole circuit used folded cascode topology to reduce the headroom voltage, and hence power consumption.
References
Shih-Chieh Shin, Ming-Da Tsai, Ren-Chieh Liu, Kun-You Lin, and Huei Wang.: A 24- GHz 3.9-dB NF Low-Noise Amplifier Using 0.18 µm CMOS Technology. J. IEEE Microw. and Wireless Compon. Lett. 15, (2005)
F. Mahmoudi and C. Salama.: 8 GHz, 1 V, high linearity, low power CMOS active mixer. in Proc. IEEE Radio Freq. Integr. Circuits Symp. Dig (2004)
N. Poobuapheun, W.-H. Chen, Z. Boos, and A. Niknejad.: A 1.5-V 0.7–2.5-GHz CMOS quadrature demodulator for multiband directconversion Receivers. IEEE J. Solid-State Circuits. 42, 1669–1677 (2007)
Y. Ding and R. Harjani.: High-Linearity CMOS RF Front-End Circuits. New York: Springer-Verlag, 2005
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