1. BB130 Contribution OMEGA PLL, CLPS Transceiver & Receiver
Ludovic Raux, Damien Thienpont
7 novembre 2017

2. Tx and Rx
30 x 115 μm²
100 x 280 μm²

3. Tx and Rx: specification
See Paulo Moreira’s presentation at Ecole Micro Benodet
Compatible with CERN protocol
Rad hard by design
Current strength : 0,5 to 4 mA
Pre-emphasis strength: 0,5 to 4 mA;
Pre-emphasis pulse width
Nominal: 120ps, 250ps, 380ps
Slow corner: 170ps, 350ps, 520ps
Fast corner: 100ps, 190ps, 280ps

4. Tx and Rx: simulation No noisy digital input
Current strength = 2,5mA, PE strenght = 2 mA, PW = 3 (max)
1,28 GHz, Cl=5pF
VCM = 570mV(T), 515mV(S), 645mV(F)
Ampl Tx = 262mV(T), 170mV(S), 330mV(F)
DutyCycle Rx = 50 <+/-2,5%
Latency = 220ps(T), 400ps(S), 80ps(F)
Jitter Tx = ~ 100 fs(T), jitter outRx = ~800 fs(T)

5. PLL
320 x 710 μm²

6. PLL: versatile architecture
Charge Pump: Icp tunable over 5 bits + 5 bits for CP BW
Low Pass Filter: R = 500 to 7500 Ohms, C = 100 or 200 pF
VCO: low gain or high gain (1 bit)
Divider: from 2 to 32
Probe: from 40 MHz to 1,28 GHz
ON/OFF PLL bit
External VCO voltage can be applied to improve lock time
All subparts onto Deep N-Well separated with high resistive substrate
Power supply = 1,2 V; 1,8 mA (vdd); 2,8 mA (vddd)
Dimension: 320x710 μm²

7. PLL: 40 MHz input clock 40MHz input Clpf = 110pF, Rlpf=2500, ICP=10uA
Lock time: 3us(T), 5us(S), 4us(F)
PERIOD_JITTER w/o noise
VCO Clk: 0,6 ps(T); 0,7 ps(S); 0,6 ps(F)
Fb. Clk: 0,2 ps(T); 4 ps(S); 0,6 ps(F)
PERIOD_JITTER w/ noise
VCO Clk: 0,8 ps
640M Clk: 2 ps
320M Clk: 2,4 ps
160M Clk: 2,9 ps
40M Clk: 3,4 ps
NOISE_JITTER
VCO Clk: 9 ps
Fb. Clk: 12 ps

8. PLL: 160 MHz input clock 160MHz input Clpf = 200pF, Rlpf=500, ICP=12uA
Lock time: 2us(T); 6,5us(S); 4us(F)
PERIOD_JITTER w/o noise
VCO Clk: 0,5 ps(T); 1,7 ps(S); 0,7 ps(F)
Fb. Clk: 9 ps(T); 17 ps(S); 7 ps(F)
PERIOD_JITTER w/ noise
VCO Clk: 1,5 ps
640M Clk: 1,6 ps
320M Clk: 4 ps
160M Clk: 7 ps
NOISE_JITTER
VCO Clk: 13 ps
Fb. Clk: 20 ps

9. SAR ADC 11 bits
40M sampling, asynchronous, important spec: good DNL, 2 ou 3 versions de capa array

10. Noise model
Dans les fichiers model spectre, il faut éditer le cr013g_2d5_v1d4.scs et changer noimod=2 par noimod=3

11. TV2:mesure vs. BSIM vs. SPICE2

12. Floorplan 1 or 2 diff. inputs ADC clock, 40M (1 or 3)
PLL input clock, 40M to 160M or more (1 or 2)
2 diff. outputs
ADC serialized output (?) (2 + 1 rather than 11)
PLL Clock probe
Slow control
Triple Voting cells
10 I/Os
1500x2500 μm²
62 PADS

13. Floorplan: alternative