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Advanced Computer Architecture Lecture 14

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Presentation on theme: "Advanced Computer Architecture Lecture 14"— Presentation transcript:

1 Advanced Computer Architecture Lecture 14
Project 4 review Write-back cache correction Write buffer Performance Lillevik s06-l14 University of Portland School of Engineering

2 Project 4 team review Team Dog Lillevik 437s06-l14
University of Portland School of Engineering

3 Cache block diagram R/W# Main Driver System enable Bus Control enable
tag R/W# Lillevik s06-l14 University of Portland School of Engineering

4 Find types of cache in PC?
Memory CPU End of a bus Veda, sound, net DMA Wireless, CD, HD Lillevik s06-l14 University of Portland School of Engineering

5 Write-back, cache hit Read Write Data provided by cache memory Fast
Data written to cache (fast) Data NOT written to memory, inconsistency exists Lillevik s06-l14 University of Portland School of Engineering

6 Write-back, cache miss Two cases
Memory and cache consistent Memory and cache inconsistent (cache has correct data) Called modified Called dirty All misses to inconsistent cache and memory require a write-back cycle first Lillevik s06-l14 University of Portland School of Engineering

7 Write-back, read miss Cache consistent Cache inconsistent
Data provided by main memory (slow) Data also written to cache (update) Cache inconsistent Data in cache written to memory (slow): WB Lillevik s06-l14 University of Portland School of Engineering

8 Write-back, write miss Cache consistent Cache inconsistent
Data written to cache (fast) Data NOT written to memory, inconsistency exists Cache inconsistent Data in cache written to memory (slow): WB Lillevik s06-l14 University of Portland School of Engineering

9 Write-back, read hit R/W# Main Driver System enable Bus Control enable
Cache Control Driver R/W# System Bus enable enable tag R/W# Lillevik s06-l14 University of Portland School of Engineering

10 Write-back, write hit R/W# Main Driver System enable Bus Control
Cache Control Driver R/W# System Bus enable enable tag R/W# Lillevik s06-l14 University of Portland School of Engineering

11 Write-back, read miss Memory consistent R/W# Main Driver System enable
Cache Control Driver R/W# System Bus enable enable tag R/W# Lillevik s06-l14 University of Portland School of Engineering

12 Write-back, read miss Two steps: write-back and memory read
Memory inconsistent Main Cache Control Driver R/W# System Bus enable enable tag R/W# Lillevik s06-l14 University of Portland School of Engineering

13 Write-back, write miss Memory consistent R/W# Main Driver System
Cache Control Driver R/W# System Bus enable enable tag R/W# Lillevik s06-l14 University of Portland School of Engineering

14 Write-back, write miss? Two steps: write-back and write cache
Memory inconsistent Main Cache Control Driver R/W# System Bus enable enable tag R/W# Lillevik s06-l14 University of Portland School of Engineering

15 Cache example CPU: our B2Logic model Memory of 32 words
Cache of 8 words Direct mapped Cache and memory at an initial state Lillevik s06-l14 University of Portland School of Engineering

16 Initial memory contents
Adr Data 1 2 3 4 5 6 7 8 9 A B C D E F Adr Data 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Cache Indexb Tagb Data 000 10 001 01 09 010 0A 011 13 100 0C 101 15 110 11 1E 111 17 Lillevik s06-l14 University of Portland School of Engineering

17 Complete the table? Instruction Tagb Indexb Hit type Data 51700 10 111
RH 17 60955 50F00 611AA 50900 51C00 6145A 51100 602A5 Lillevik s06-l14 University of Portland School of Engineering

18 Final memory contents? Memory Cache Adr Data Adr Data Indexb Tagb Data
1 2 3 4 5 6 7 8 9 55 A B C D E F Adr Data 10 11 aa 12 13 14 5a 15 16 17 18 19 1A 1B 1C 1D 1E 1F Cache Indexb Tagb Data 000 001 01 55 010 011 100 10 5a 101 110 111 0f Lillevik s06-l14 University of Portland School of Engineering

19 Write-through write hit
SLOW !! Main Cache Control Driver R/W# System Bus enable enable tag R/W# Lillevik s06-l14 University of Portland School of Engineering

20 Write buffer Goal: speed up writes to memory Design
Add write buffer (register) between cache and memory Once register written, Ack CPU Write to memory overlaps next instruction, hides memory access time Design Register often a FIFO Typical depth of 4 lines Lillevik s06-l14 University of Portland School of Engineering

21 Write buffer, write hit (or miss)
Write-through cache Write buffer, write hit (or miss) Main Cache Control Driver enable R/W# tag System Bus Buffer Lillevik s06-l14 University of Portland School of Engineering

22 Memory write overlaps next instruction
Write buffer timing 1st write 2nd write read hit CPU Ack R/W# 1st write 2nd write Memory write overlaps next instruction Lillevik s06-l14 University of Portland School of Engineering

23 Memory performance Metrics: latency, bandwidth Average latency, L
Assumes cache latency same for reads and writes Expression may be applied recursively Lillevik s06-l14 University of Portland School of Engineering

24 Find average latency? CPU clocked at 1.5 GHz
DDR memory speed is 500 MHz Cache cycle time is 100 ps Hit rate is 0.95 Lillevik s06-l14 University of Portland School of Engineering

25 Write buffer performance
Write-through cache Write buffer performance Reads: occur with probability r Writes: occur with probability (1-r) Four possibilities (probabilities) RH = rh = cache hit, Lc RM = r(1-h) = cache miss, Lm WH = (1-r)h = cache hit, Lc WM = (1-r)(1-h) = cache hit, Lc Due to buffer Lillevik s06-l14 University of Portland School of Engineering

26 Find write buffer performance?
Lillevik s06-l14 University of Portland School of Engineering

27 Find average latency? Direct mapped cache, write buffer
CPU clocked at 1.5 GHz DDR memory speed is 500 MHz Cache cycle time is 100 ps Hit rate is 0.95 One write to every three reads Lillevik s06-l14 University of Portland School of Engineering

28 Lillevik s06-l14 University of Portland School of Engineering

29 Find types of cache in PC?
Memory: L1, L2 (data and instruction) Hard drive CD drive Modem, Ethernet controller Graphics controller Serial, parallel port, USB Printer Lillevik s06-l14 University of Portland School of Engineering

30 Find average latency? Lillevik 437s06-l14
University of Portland School of Engineering

31 Find write buffer performance?
Lillevik s06-l14 University of Portland School of Engineering

32 Find average latency? Lillevik 437s06-l14
University of Portland School of Engineering

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