1. 3.2 Shift Register Basic shift register function
Serial in / serial out shift registers
Serial in / parallel out shift registers
Parallel in / serial out shift registers
Parallel in / parallel out shift registers
Bidirectional shift registers
Shift register applications

2. Sequential Logic Circuits
Combinational outputs
Memory outputs
Combinational logic
Memory elements
Inputs
Sequential circuit = Combinational logic + Memory Elements
Current State of A sequential Circuit:
Value stored in memory elements (value of state variables).
State transition:
A change in the stored values in memory elements thus changing the sequential circuit from one state to another state.

3. Registers
A register is a memory device that can be used to store more than one-bit information
A register is usually realized as several flip-flops with common control signals that control the movement of data to and from the register

4. Registers
An n-bit register is a collection of n D flip-flops with a common clock used to store n related bits.
Example:
74LS175 4-bit register
74LS175 1D 1Q D Q
CLR Q
/1Q
CLK
CLR 4Q 3Q 2Q 1Q
74LS175 1D 2D 3D 4D 2Q 2D D Q
CLR Q
/2Q 3Q 3D D Q
CLR Q
/3Q 4Q 4D D Q
CLR Q
/4Q
CLK
/CLR

5. Shift Registers
Multi-bit register that moves stored data bits left/right ( 1 bit position per clock cycle)
Shift Left is towards MSB
LSI
Q3 Q2 Q1 Q0
LSI
Q3 Q2 Q1 Q0
Shift Right (or Shift Up) is towards MSB
RSI
Q3 Q2 Q1 Q0
RSI
Q3 Q2 Q1 Q0

6. Basic Shift Register Functions
Consist of an arrangement of flip-flops
Important in applications involving storage and transfer of data (data movement) in digital system
Used for storing and shifting data (1s and 0s) entered into it from an external source and possesses no characteristic internal sequence of states.
D flip-flops are use to store and move data

7. The flip-flop as a storage element
Still remember the truth table for D flip flop?
D CLK/C Q Q’_________________
↑ 1 0 SET (stores a 1)
↑ RESET (stores a 0)

8. The flip-flop as a storage element
When a 1 is on D, Q becomes a 1 at triggering edge of CLK or remains a 1 if already in the SET state
When a 0 is on D, Q becomes a 0 at triggering edge of CLK or remains a 0 if already in the RESET state

9. Types of Shift Register
Serial In / Serial Out Shift Registers (SISO)
Serial In /Parallel Out Shift Registers (SIPO)
Parallel In / Serial Out Shift Registers (PISO)
Parallel In / Parallel Out Shift Registers (PIPO)

10. Basic data movement in shift registers (Four bits are used for illustration. The bits move in the direction of the arrows.)

11. Serial In, Serial Out Shift Register (SISO)
SRG n
> SI SO
D Q
CLK
SERIN
CLOCK
SEROUT
For a n-bit SRG:
Serial Out = Serial In delayed by n clock period
4-bit shift register example:
serin:
serout:
clock:

12. Serial In, Serial Out Shift Register (SISO)

14. Serial In, Serial Out Shift Register (SISO)
FF0
FF1
FF2
FF3
Clear
1010
101 10 1 00
000
0000

15. Serial In, Serial Out Shift Register (SISO)
Clk
FF0
FF1
FF2
FF3
Clear 1 2 3 4 5
101100 6
10110 7
1011 10 8
101
110 9
1110
01110 11
001110

16. Serial In, Serial Out Shift Register (SISO)
FF0
FF1
FF2
FF3
Clear 1
101100
10110
1011 10
101
110
1110
01110
001110

18. Serial In, Serial Out Shift Register (SISO)

19. Serial In, Parallel Out Shift register (SIPO)
SRG n
> SI 1Q 2Q nQ
D Q
CLK
SERIN
CLOCK nQ 2Q 1Q
(SO)
Serial to Parallel Converter
Example: 4-bit shift register
serin:
1Q:
2Q:
3Q:
4Q:
clock:

20. Can u see the difference?
D Q
CLK
SERIN
CLOCK
SEROUT
D Q
CLK
SERIN
CLOCK nQ 2Q 1Q

21. Serial In, Parallel Out Shift register (SIPO)
Data bits entered serially (right-most bit first)
Difference from SISO is the way data bits are taken
out of the register – in parallel.
Output of each stage is available

22. Example : The states of 4-bit register (SRG 4) for the data input and clocks waveforms.
Assume the register initially contains all 1s

23. 4-bit parallel in/serial out shift register (PISO)

24. 4-bit parallel in/serial out shift register (PISO)
When signal = 1,
SHIFT
When signal = 0,
 LOAD

25. 4-bit parallel in/serial out shift register (PISO)
When signal = 0,
LOAD
G1 – G3
enabled

26. 4-bit parallel in/serial out shift register (PISO)
When signal = 1,
SHIFT
G4 – G6
enabled

27. 4-bit parallel in/serial out shift register (PISO)

28. Can you try and trace the output for each FF stage until you get Q3?

29. Let’s try to trace this one first…1 1
Assume that the signal has values
for 6 respective clock cycle
For the parallel data input
Assume D0 = 1, D1 = 0, D2 = 1, D3 = 0

30. Let’s try to trace this one first…1 1 1
CLK 1,
Signal = 0
G1 – G3
Will get value = 1
G4 – G6
Will get value = 0
Referring to the AND gate theory,
All gates that receives “0” values at shift/load can be ignored.

31. Let’s try to trace this one first…1 1 1 1 1
Now, AND the shift/load with respective Data bit, D0 – D3

32. Let’s try to trace this one first…1 1 1 1
CLK 2,
Signal = 1
G1 – G3
Will get value = 0
G4 – G6
Will get value = 1
Referring to the AND gate theory,
All gates that receives “0” values at shift/load can be ignored.

33. Let’s try to trace this one first…1 1 1 1 1
Now, AND the shift/load value with
Respective data that goes into G4, G5, G6

34. How do you put it in table?
For the parallel data input
Assume D0 = 1, D1 = 0, D2 = 1, D3 = 0
Clk
Shift/Load
Active signal Q0 Q1 Q2 Q3
Clear 1
LOAD 2
SHIFT 3 4 5 6

35. Can you try and trace the output for each FF stage until you get Q3?

36. Parallel In, Serial Out Shift Register (PISO)
CLOCK
LOAD/SHIFT
SERIN 1Q S
D Q
CLK 1D L 2Q S
D Q
CLK 2D L
Parallel to Serial Converter
Load/Shift=1
Di Qi
Load/Shift=0
Qi Qi+1 NQ S
D Q
CLK
SEROUT ND L

37. Parallel In, Parallel Out Shift Register (PIPO)
Immediately following simultaneous entry of all data bits, it appear on parallel output.

38. Parallel In, Parallel Out Shift Register (PIPO)
CLOCK
LOAD/SHIFT
SERIN S
D Q
CLK 1Q 1D L S
D Q
CLK 2Q 2D L
General Purpose:
Makes any kind of (left) shift register S
D Q
CLK NQ ND L

39. Parallel In, Parallel Out Shift Register (PIPO)

40. Bi-directional Shift Registers
Data can be shifted left
Data can be shifted right
A parallel load maybe possible
74HC194 is a bidirectional universal shift register

41. Bi-directional Universal Shift Registers
4-bit Bi-directional Universal (4-bit) PIPO
CLK
CLR S1 S0
LIN
D QD
C QC
B QB
A QA
RIN 11 1 10 9 7 6 4 5 3 2 12 13 14 15
74x194
Modes:
Hold
Load
Shift Right
Shift Left
R L
Mode Next state
Function S1 S QA* QB* QC* QD*
Hold QA QB QC QD
Shift right/up RIN QA QB QC
Shift left/down QB QC QD LIN
Load A B C D

42. Four-bit Johnson counters
Serial output connected back toserial input
The complement of the output (Q’) is fedback into 1st FF.

43. Five-bit Johnson counters

44. A 10-bit ring counter
Assume initial state :

45. Shift Register Applications
State Registers
Shift registers are often used as the state register in a sequential device. Usually, the next state is determined by shifting right and inserting a primary input or output into the next position (i.e. a finite memory machine)
Very effective for sequence detectors
Serial Interconnection of Systems
keep interconnection cost low with serial interconnect

46. Shift Register Applications
Bit Serial Operations
Bit serial operations can be performed quickly through device iteration
Iteration (a purely combinational approach) is expensive (in terms of # of transistors, chip area, power, etc).
A sequential approach allows the reuse of combinational functional units throughout the multi-cycle operation

47. Shift Register Applications Example: Serial Interconnection of Systems
CLOCK
Transmitter
Receiver
Control
Circuits
Control
Circuits
/SYNC
Parallel Data from
A-to-D converter
Parallel Data to D-to-A converter
Serial-to-parallel converter
Parallel-to-serial converter
Serial DATA n
One bit n

48. Shift Register Applications Example: The shift register as a time-delay device