1. J. J. John on behalf of the team
Next steps 16 June this version is the minutes – with notes added (in pink)
J. J. John on behalf of the team

2. Agenda Review current work and discuss steps for next week
Update on datapath blocks (Kevin and Wojtek)
Update on CHESS-2 data emulator (Tianbo)
Overview of Top_Logic (Weiguo)
Any other business

3. Ongoing and new actions
new actions in blue
updates in pink
(actions which were already done last week have been removed)
Matt: [ongoing] adapt the ITSDAQ DIO code for the ABCN’, to remove pad primitives. – Matt sent apologies for today (had ITk activity co-ordinators’ meetings). Code changes were nearly done. Jaya John to follow up current status.
Kevin and Wojtek: [done] send Cluster Finder interface questions to Aditya Narayan at Penn. Aditya replied answering Kevin’s questions. See slide 4 of these minutes and Kevin’s Readout Adaptor presentation.
Kevin: contact Paul to ask if the HCC relies in any way on the value 0x7FD (which the ABC130* uses to represent “no hits”). Check that Kevin’s proposed single packet (11 bits only) will work fine with the HCC, to represent “no hits” for CHESS-2.
Tianbo: [ongoing] working on CHESS-2 Data Emulator. – See slide 5 of these minutes and Tianbo’s Emulator slides.
Jaya John: [ongoing] prepare a tidied-up block diagram for the ABCN’ – In progress, working from source code which has some differences compared to the high-level ABC130* block diagram.
Jaya John: [ongoing] understand CHESS-2 configuration registers and how to map them into the ABCN’ memory map. – In progress: gathered details of CHESS-2 registers from CHESS-2 designers.
Matt: send link to Kevin for: (b) test bench code and (c) where the mappings are made in the package files (nexys/src?) = constraint file – Jaya John to follow up.
Weiguo: [done] walk us through how the Top_Logic block works and its interfaces.
Weiguo: add a state transition diagram to the Top_Logic slides.

4. Notes for Readout Adaptor presentation
Kevin replaced the Cluster Finder of the ABC130* with a Readout Adaptor block for the ABCN’. This will enable us to use the ABC130*’s Readout block as it is.
The Readout Adaptor’s job is to segment the 112-bit wide CHESS-2 data into 12-bit packets: 11 bits of data plus a stop bit.
Kevin showed simulations of different CHESS-2 data sets. Note that the Cluster Write Enable goes low for one clock between successive hits – this is needed by the Readout Block to get its timing.
We discussed removing Data Valid from the output data stream. This should be possible, but Kevin will check with Paul about HCC expectations about how to represent no hits.
Currently the ABC130* represents the no hits condition with hex 7FD, which is a cluster value which is impossible to produce in the ABC130*. Does the HCC rely on the value 0x7FD?
Otherwise, Kevin’s proposal is to use an 11-bit-only packet (stop bit set) to represent no hits – a single packet. Any valid CHESS-2 data must consist of at least 2 11-bit packets, so that is how we’d distinguish valid hit data.
The Readout Block has a FIFO, implemented as a behavioural description. Let’s see if will synthesise and work in the FPGA setting. We can replace it with a Xilinx-specific FIFO if need be.

5. Notes for CHESS-2 Data Emulator presentation
Tianbo designed and tested the first and second steps of emulator plus a test bench (generator).
The first step adds 3 to the column address and 11 to the row address on each 320MHz clock cycle, to cycle through a series of different values. The sequence can be reset.
The 2nd step uses a linear feedback shift register (LFSR) to generate a stream of pseudo- random data. The sequence repeats with a certain period -- see slides.
We think that we can ignore the BC clock for the LFSR approach. It seems like a reasonable choice for now not to synchronise the pseudo-random data to BC.
We discussed the limitations of pseudo-random data generated with a LFSR. Right now, the main thing is to have some sequence of data with the correct timing, so this is achieved.
Later, we may want to have more randomness, or at least less correlation between successive hit patterns.
LFSR could have more bits, if we have enough FPGA resources for this? E.g. 13 x 8 bits may be possible.
If we added more XOR gates, could have less correlation between adjacent numbers.
Kevin suggested checking Wikipedia for examples of producing longer sequences.

6. Notes for Top_Logic presentation
Top_Logic is a state machine processing incoming PR and LP triggers and register read requests.
Note, PR = Priority Readout request, corresponds to R3 trigger for ABC130 LP = Lower Priority readout request, corresponds to L1 trigger for ABC130.
Top_Logic co-ordinates these blocks: L0L1TOP, the Cluster Finder and the Readout block.
Slide 6 shows the conditions which cause state transitions.
For the state names, PCSS means process. For example, PR_PCSS means “process PR trigger”.
Weiguo said he could add a state transition diagram to his slides.
Queen Mary update
Rodrigo Gamboa of QMUL attended. We discussed CHESS-1 testing: Rodrigo is getting set up for testing CHESS-1 with Atlys at the moment. He’ll begin by using the Tester daughterboard.