2. Design and implementation of a frequency hopping transceiver on a sdr kit Phase-V
ADVISOR
Wg Cdr Sohail Ahmed
CO-ADVISOR
Wg Cdr M. Ajmal
STUDENT
Plt Off Kamran Zia (15463)
I am po kamran zia and I am going to present my mid term presentation on design…….
My advisor is wc sohail ahmed and my co advisor is wc m.ajmal

3. Sequence Aim of project SDR Kit introduction Background Milestones
Frame synchronization
Symbol synchronization
Hopping synchronization
Final Specifications
Goals achieved
Questions
This would be the sequence of my presentation

4. Aim of project
Design and implementation of a frequency hopping transceiver with symbol and hopping synchronization on two Software Defined Radio development kits.
The aim of the project is to design and implement ……………………….

5. Software Defined Radio (SDR)
Radios that provide software control of a variety of
Modulation techniques
Filtering operations
Coding and Encryption etc
Replace dedicated hardware with general purpose digital signal processing engines (DSP) for digital baseband processing
It uses general purpose DSP engines instead of dedicated hardware. They are the radios that can provide control of a variety of mod. Tech. wide and narrow band ops and coding and encryption
This allows the radio to be reconfigured with the help of software
The reconfiguration may be of modulation technique , bandwidth ,coding , encryption and etc

6. SDR Kit Introduction SDR Development platform by Lyrtech
consists of three modules:
Digital signal processing module
DSP (TMS320DM6446)by Texas Instruments
FPGA (Virtex-4 Sx35) by Xilinx
Data conversion module
RF module
Currently available SDR kit by Lyrtech
Consists of three parts
DIGITAL PROCESSING MODULE which consist of DSP and fpga
DATA conversion module containing ADC and DAC cards for converting form of signal
RF module used for transmitting the signal

7. Background Continuation project
Phase I : Design of a frequency hopping modem in Matlab/Simulink was given
Phase II : Frequency hopping transmitter was implemented on SDR kit
Phase III : Receiver was implemented and a simplex link was established between two SDR kits
This is a continuation project.
So giving you the ground what previously has been done is very important
During phase 1 done in 65ec design of frequency hopping modem in matlab and simulink was given.
in phase 2 A frequency hopping transmitter was implemented on SDR kit by 2 students of 67 ec
In phase 3 receiver was implemented and full duplex link was established b/w two sdr kits 7

8. Background (Cont’d)
Phase IV : Hopping synchronization was achieved on single kit using FFT algorithm
This phase of the project aims at:
Developing a symbol synchronization algorithm for communication between two SDR kits
Improvement of frame synchronization
Improvement and implementation of hopping synchronization on two SDR kits
In phase 4 hopping sync was done on a single kit using FFT algorithm for 7 hopping frequencies.
This phase of the project aims at implementing a transceiver with mfsk mod with m>2 and implemnting a hopping sync tech which is workable for any no of hopping frequencies
Check how mfsk is better than 2fsk
A frequency hopping transmitter was implemented by 2 students of previous semester on SDR kit
In this phase a receiver for frequency hopping system is to be implemented

9. Study Phase Requisite literature has been studied
Training has been done on softwares like:
Matlab/Simulink
Xilinx system generator for DSP
Xilinx AccelDSP
Xilinx foundation ISE
Code composer studio (TI)
Understanding the working of SDR kit and previous models

10. Frequency Hopping Transmitter
Audio Input
Modulation(FSK)
DUC
Hopping
Carrier
DSP module
this is an overview of the transmitter that was implemented.
Audio input was modulated and digitally up converted by a hopping carrier to shift the signal to Intermediate frequency,
then digital to analog conversion was done
and finally for RF transmission ,the analog signal was mixed with RF oscillator
RF module
Data Conv. module
Antenna
RF Processing
D / A

11. Frequency Hopping Receiver11
RF Module
Data conversion Module
Antenna
RF down
conversion
A/D
Hopping
Sync.
This illustrates aim of the project.
The transmitted signal is firstly downconverted to IF by RF module
the signal is then sampled by A/D converter
which is then followed by digital downconversion and demodulation in DSP module
Audio output
Demodulation
DDC
DSP Module

12. MATLAB and Simulink families
Algorithm development and Model-Based Design with
MATLAB and Simulink families 12
Lyrtech FPGALink™
Lyrtech DSPLink™
Xilinx System
Generator for DSP
The MathWorks
Real Time Workshop
Xilinx
Foundation ISE
Texas Instruments
Code Composer
Studio
This is an implementation architecture of SDR
Initially, an FPGA model is bulit using matlab in System generator block set. Then the VHDL code for fpga model is built by system generator.
The dsp model is bulit using matlab in simulink communication and signal processing block set and the C code for the dsp model is built using real time workshop.
XILINX ise foundation 9.2i and codecomposer studio 3.3 are used to provide platform for debugging synthesis and compilation of models. The codes are then downloaded on to SDR kit for execution of models.

13. Frame Synchronization
Finding the start of each message data block
The receiver finds the SOF(start of frame) bits by analyzing the data and extracts the message bits from the frames
Synchronization operations are the most the important operations in digital communication system.In an SDR, messages come in packets, and each packet has a header (that is located in some agreed-upon place within each data block). The process of identifying where the header appears inthe received signal is called frame synchronization. Previously a 4 bit start of frame was used as header which has been changed to 8 bits as previously no coding was applied. Voice is quantized to 16 bits and the channel coding technique doubles the number of bits so 32 bit message is concatenated with a 8 bit header which has to be identified at the receiver and the message is extracted. The sequence 0 six ones and 0 has been selected as the channel coding scheme implemented doesn’t allow this sequence to appear in the data.
8 BIT SOF
12 BIT MESSAGE

14. Frame Synchronization (cont’d)
Demodulated Bitstream
Serial to parallel conversion
Bit Slicing
Parallel search (M code)
To DSP processor
Data Extractor

15. Symbol Synchronization
Finding the correct start of the symbol at the receiver
Demodulation depends on symbol synchronization
Continuous symbol misalignment due to clock mismatch
Feedback mechanism for continuous symbol matching
Data is modulated and transmitted in the form of symbols in digital communication. In my design FSK modulation is utilized so I have two symbols that are the FSK frequencies. I have utilized 128 samples per symbol . At the receiver it is very important to find the correct start of symbol. This is required for correct demodulation of the data. If the symbol is not matched then demodulation could not be done properly. There was a continuous symbol misalignment because of the clock mismatch between the transmitter and receiver. For correction a feed back mechanism was required to make receiver continuously match the transmitted symbol

16. Symbol Synchronization (cont’d)
Properly synchronized receiver window
Incorrect synchronization at the receiver
S1 and S2 interfere
These figures show the difference between a properly synchronized receiver window and a poorly synchronized window. Note that in the first figure, there is no ISI between any two symbols, whereas in the second figure, there is an initial offset due to incorrect start by the receiver. looking at the first window of the MF there is Inter symbol interference between S1 and S2. Similarly there is ISI between the two symbols in each window. The receiver doesn’t know when to start and thus this problem takes place. If the transmitter sampling clock is at a slightly different frequency than the receiver sampling clock
The windows will drift
Worse than an initial offset
INITIAL OFFSET
ISI

17. Data aided Symbol Synchronization
FSK Demodulator
Received bitstream
Parallel search
(header bits)
Data is demodulated and bitstream is received. The received bitstream is presented to frame sync block where parallel search of header bits is carried out … if these header bits are missed receiver gets the indication the symbol is not matched because of which the demodulation is corrupted and header bits are missed. So it shifts the integration window to find the correct start of symbol.
If Frame header not found
Symbol Synchronizer

18. Early Late Gate Symbol Synchronization18
Early gate
Late gate
(a)
time
Delayed FSK Symbol
(b)
time
Advanced FSK Symbol
(c)
time

19. Early late gate Symbol Synchronization
Number of samples per symbol are divided into two equal parts and integrated separately
The two integration results are taken as early and late gate values
Difference of early and late gate values is computed to find symbol timing mismatch
Difference value tells the symbol synchronizer to shift the integration window to the correct start of symbol

20. Hopping Synchronization
Hopping synchronization can be achieved in three different ways
Burst synchronization
Camp and wait
Fast Fourier Transform (FFT) based synchronization

21. Burst synchronization21
Divided into two modes:
Handshake
Two radio sets exchange Request and Acknowledgement signals to ensure alignment before switching to the Hop Mode
Hopping mode
Normal transmission mode
Any phase error between the two radio sets is corrected during fine synchronization

22. Hopping Error PN sequence generated at the receiver
Propagation delay between transmitter and receiver during handshake introduces hopping error
The hopping error needs to be corrected for hopping synchronization
In handshake mode the receiver must have the same sequence as the transmitter so that they can hop together at same frequency. So same pn sequence has been generated at the receiver. The tx sends a RTH signal to receiver and starts hopping . As soon as receiver receives the signal it also starts hopping but due to the propagation delay there would be a phase difference between tx and rx. As the second kit is not available so to have the effect of propagation delay a variable delay has been introduced in dsp model to achieve the phase difference b/w tx and rx. The delay introduces a small hopping error between tx and rx.
Local frequencies F1 F2 F3
Received frequencies Ø F1 F2 F3

23. Phase Lock Loop {Cos (2π (f1-f0)t)+Cos(2π(f1+f0)t)}/2 Cos (2πf0t)
MULTIPLIER PHASE DETECTOR
LOOP FILTER
This is the block diagram of phase lock loop
Cos (2πf1t)
DISCRETE TIME VCO

24. Hopping Error Detection and Correction
First step at the receiver is to detect hopping error
Hopping error is detected using multiplier correlator
Error could be used to slow down or increase the rate of PN sequence generation for hopping error correction
It needs to be transferred to DSP processor

25. Modified Phase Lock Loop
Signal from ADC
LPF
Direct Digital Synthesizer
PN sequence
DSP Processor

26. Camp and Wait
Receiver waits for a specific frequency to go into the hopping mode
Starts hopping as soon as it receives that frequency
Hopping error still exists that needs to be corrected

27. Camp and Wait (cont’d) TRANSMITTER RECEIVER 1 2 3 4 5 1 2 3 4 5
In this method, the receiver waits for a known hopping frequency. The frequencies for which the receiver is waiting can be more than 1. As soon as a signal at that frequency is detected, the receiver aligns itself with the received signal and starts hopping its frequency.
Search method reduces the frequency uncertainty to less than one hop. But the starting edges of the received and local frequencies may still not be aligned fully. Acquisition circuit aims to align the starting instants which is similar to Phase Lock Loop.

28. FFT based Hopping Synchronization
Fast Fourier Transform is utilized for detection of incoming frequencies
Frequencies are generated at the receiver with direct digital synthesizer (DDS)
Dehopped signal is sent to the low pass filter for removing high frequency component and demodulation

29. FFT based Hopping Synchronization
To Demodulator
Detection of frequency
Signal from ADC
64 point FFT
64 point FFT has been used to detect the frequency, and the frequency once detected enables the PN sequence which runs the Direct digital synthesizer. The output of the synthesizer is multiplied with the signal which converts it to baseband signal and the signal is routed towards the Low pass filter.
Frequency tuning word
Direct Digital Synthesizer

30. Final Specifications PARAMETER VALUE Audio sampling rate 15.625 KSPS
Voice quantization
16 bits
DSP to FPGA ( sample rate)
No. of start of frame bits
8 ( ‘ ’ )
Bit rate
312.5 Kbps
FPGA Clock frequency
80 MHz

31. Final Specifications (Cont’d)
PARAMETER
VALUE
Channel Spacing
1.25 MHz
FFT
64 point(frequency resolution of 1.25 MHz)
Hopping Rate
20,50,100 hops/sec
Number of Hopping Frequencies 7
Hopping Bandwidth
20 MHz (20-40 MHz)
Channel Coding No

32. Goals Achieved Symbol Synchronization Improved Frame Synchronization
FFT based Hopping Synchronization
Transmission and reception of voice and data between two SDR kits in hopping mode

33. Challenges One of the SDR kit was not available till 12th week
There were no means to analyze FPGA in real time
Only evaluation version of softwares were available
Synchronization problems due to clock mismatch
Failure to achieve fine hopping synchronization because of slow transfer rate between DSP processor and FPGA

34. Recommendations
Optimization and Pipelining of FFT for faster detection of frequencies
Development of FH transceiver on national instruments IF transceiver card
Procurement of JTAG Emulators and Chipscope Pro for analyzing FPGA in real time

35. References
Lyrtech ,SFF SDR Development Platform Model-based Design Guide
Xilinx Corp., System Generator for DSP User Guide
Xilinx Corp., AccelDSP User Guide
Xilinx Corp., Foundation ISE User Guide
Design and implementation of frequency hopping software defined radio” (BE project), by Flying officer Umair Ahmed (68 EC)
John G. Proakis “Digital Communications”, 2nd Edition, McGraw Hill
Heinrich Meyr “Digital Communication Receivers - Synchronization, Channel Estimation, and Signal Processing”

36. Thank you

37. QUESTIONS