1. With Thermal Code inputs
Systolic Sorter
With Thermal Code inputs

2. Overview What is the Min/Max cell What is the Sorter
Why are you doing this
What is left to do
Demos

3. Min Max Cell Inputs are in thermometer code This makes comparison easy
Let X1=0011 X2=0111
&
0011=min =max
Tradeoff is more bits/input

4. Sorter M inputs each N bits wide Inputs on right Outputs on top
Little squares are registers (we’ll get there in a bit)

5. Sorter Dataflow

6. Sorter Dataflow

7. Sorter Dataflow

8. Sorter Dataflow

9. Sorter Dataflow

10. Sorter Dataflow

11. Sorter Dataflow

12. Sorter Dataflow

13. Sorter Dataflow

14. Sorter Dataflow

15. Sorter Dataflow

16. Sorter Dataflow

17. Sorter Dataflow

18. Sorter Dataflow

19. Sorter Dataflow

20. Sorter Dataflow

21. Sorter Dataflow

22. Sorter Dataflow

23. Sorter Dataflow

24. Sorter Dataflow

25. Work With Muayad He has built same sorter with memristors
I need to calculate
Power
Area
Speed
Compare to his results

26. Left for me
Get code working
Devise decent testbench

27. Future Cells have more functionality (different functions)
External control of cells
New connections
Instructions travel with data

28. Demo Cell on FPGA Workflow on QuestaSim on (Redhad servers)
Vivado schematic
QuestaSim schematics