1. Hexagons and 8” Sensor R&D Ron Lipton
Some random thoughts and information …
We are in the process of exploring silicon sensor fabrication with Novati Inc.
They are an R&D fab, a descendent of Semitech – founded in the 80’s to collaboratively develop IC technology to compete with Japan…
Now (after 2 owners) they are owned by Tezzaron (Naperville) – with whom we have worked closely with on 3D electronics.
They are interested in sensor development, eventually through SBIR
10,000-15,000 wafer/month capacity
They have unique capabilities in wafer thinning, bonding, and interconnect that can be leveraged for future development.
Given Hamamatsu’s dominance does this make sense?
R. Lipton

2. 3D Integrated sensor/readout chip
2-tier 0.13 micron VIP chip
24 micron pitch pixels
4 micron pitch layer interconnects
192x192 pixels
34 mm
R. Lipton

3. Initial Run The initial Novati run would be: n-on-p
750 micron thick (could be thinned later?)
Leave off final aluminum, thin, implant backside and anneal – not in budget
Focused on test structures – validate process, low leakage current, carrier lifetimes
However there is a lot of space on an 8” wafer
Can add hexagon structures and phase 2 tracker structures
If initial run works and SBIR approved, build SOI wafers with 100, 200 micron thick sensor regions in the next run.
R. Lipton

4. 4 cm
R. Lipton

5. Hexagon Spreadsheet
For some reason I made a spreadsheet that calculates tiling of arbitrary hexagons and generates macro code to generate a gds silicon layout file.
R. Lipton

6. Hexagons
1.02 cm
R. Lipton

7. Hex on 8” wafer
15.6 cm
R. Lipton

8. Center Region
Frame
P-stop
R. Lipton

9. Edge Region
R. Lipton

10. Capacitance Extraction
Hexagon geometry:
Metal area – cm^2/hexagon
Gap – 30 microns
Metal overhang – 5 microns
This test model has 100 micron silicon thickness – so the backplane capacitances have to be divided by 2. This was a sanity check using existing parameters.
Use Cadence capacitance extraction tools
To measure coupling to neighbors and backplane
* CAPACITOR CARDS * C1 netD3 netD E-13 C2 netD0 netD E-13 C3 netD1 netD E-13 C4 netD4 netD E-13 C5 netD2 net E-11 C6 netD5 net E-11 C7 netD6 net E-11 C8 netD3 net E-11 C9 netD0 net E-11 C10 netD1 net E-11 C11 netD4 net E-11
Spice file output
Test array
~ 45.6 pf + 6*0.8pf/2