1. Principles of Computers 18th Lecture
Pavel Ježek, Ph.D.

2. Software Interrupts CPU arch. Interrupts supported by CPU ISA
instruction in
assembler
In machine
code
Instruction behavior
6502
1 vector (16 bit address of handler) at
$FFFE - $FFFF

3. Software Interrupts CPU arch. Interrupts supported by CPU ISA
instruction in
assembler
In machine
code
Instruction behavior
6502
1 vector (16 bit address of handler) at
$FFFE - $FFFF
BRK
$00

4. Software Interrupts CPU arch. Interrupts supported by CPU ISA
instruction in
assembler
In machine
code
Instruction behavior
6502
1 vector (16 bit address of handler) at
$FFFE - $FFFF
BRK
$00
JSR ($FFFE)

5. Software Interrupts CPU arch. Interrupts supported by CPU ISA
instruction in
assembler
In machine
code
Instruction behavior
6502
1 vector (16 bit address of handler) at
$FFFE - $FFFF
BRK
$00
JSR ($FFFE)
8086/88
256 vectors with fixed base address:
$0000:$0000
(1 vector = bits = segment:offset)

6. Software Interrupts CPU arch. Interrupts supported by CPU ISA
instruction in
assembler
In machine
code
Instruction behavior
6502
1 vector (16 bit address of handler) at
$FFFE - $FFFF
BRK
$00
JSR ($FFFE)
8086/88
256 vectors with fixed base address:
$0000:$0000
(1 vector = bits = segment:offset)
INT $xx
(x = 0 … 255)
$CD $xx

7. Software Interrupts CPU arch. Interrupts supported by CPU ISA
instruction in
assembler
In machine
code
Instruction behavior
6502
1 vector (16 bit address of handler) at
$FFFE - $FFFF
BRK
$00
JSR ($FFFE)
8086/88
256 vectors with fixed base address:
$0000:$0000
(1 vector = bits = segment:offset)
INT $xx
(x = 0 … 255)
$CD $xx
CALL [xx * 4]

8. Software Interrupts CPU arch. Interrupts supported by CPU ISA
instruction in
assembler
In machine
code
Instruction behavior
6502
1 vector (16 bit address of handler) at
$FFFE - $FFFF
BRK
$00
JSR ($FFFE)
8086/88
256 vectors with fixed base address:
$0000:$0000
(1 vector = bits = segment:offset)
INT $xx
(x = 0 … 255)
$CD $xx
CALL [xx * 4]
>= 80286
256 vectors:
base address given by
IDTR register

9. Software Interrupts CPU arch. Interrupts supported by CPU ISA
instruction in
assembler
In machine
code
Instruction behavior
6502
1 vector (16 bit address of handler) at
$FFFE - $FFFF
BRK
$00
JSR ($FFFE)
8086/88
256 vectors with fixed base address:
$0000:$0000
(1 vector = bits = segment:offset)
INT $xx
(x = 0 … 255)
$CD $xx
CALL [xx * 4]
>= 80286
256 vectors:
base address given by
IDTR register
CALL [IDTR + xx * 4]

10. Example of Firmware ABI via Software Interrupts
BIOS API functions/procedures
Interrupt vector
(arguments passed in registers)
Disk access – e.g. read sector
$13
Screen output – e.g. print text to screen
$10
Keyboard input – e.g. read last key pressed
$16
Get total amount of RAM installed
$12
Get memory map
$15

11. Selected Faults/Traps/Exceptions of x86 ISA
BIOS API functions/procedures
Interrupt vector
(arguments passed in registers)
Disk access – e.g. read sector
$13
Screen output – e.g. print text to screen
$10
Keyboard input – e.g. read last key pressed
$16
Get total amount of RAM installed
$12
Get memory map
$15
CPU Exception
Interrupt vector
(all push IP of faulting instruction)
Invalid opcode 6
Divide by zero (DIV0)
Alignment check
17 ($11)