1. Activities in Pavia/Bergamo on SVT strip readout and on Layer0 pixels
Luigi Gaioni, Alessia Manazza, Massimo Manghisoni, Lodovico Ratti,Valerio Re, Gianluca Traversi, Stefano Zucca
INFN Pavia, Universities of Bergamo and Pavia
SuperB Workshop
Frascati, April 4, 2011
V. Re
SuperB Workshop, Frascati, April 4, 2011

2. R&D on SVT strips and pixels
Readout chips are needed for SVT strips (layer 0-5, from short strips to long strips): we are in the process of defining the specs for these chips
R&D on advanced pixel sensors for Layer0 is in progress:
INMAPS (CMOS 0.18 mm)
Pixels based on 3D integration
CMOS 65 nm
V. Re
SuperB Workshop, Frascati, April 4, 2011

3. Specifications of readout ICs for SVT strips
New readout chips with triggered readout of hit strips with analog information are to be designed
Evaluation of existing chips (such as FSSR2) showed that none of them is able to comply with SVT specs (performance and/or functionalities)
Specs are very different from inner to outer SVT layers (signal peaking time, sensor capacitance,…) so that two different chips are most probably needed
V. Re
SuperB Workshop, Frascati, April 4, 2011

4. Noise evaluation in SVT layers: analog channel model
CD=detector capacitance+strays
RS=series resistance of the detector
CF=feedback capacitance
Cin=input capacitance
tp=peaking time
T(stp)=shaper transfer function
We assume that the main contributions come from thermal and 1/f noise in the preamplifier input device and from thermal noise in the distributed strip resistance
Noise in the detector leakage current and in the reset network not considered
V. Re
SuperB Workshop, Frascati, April 4, 2011 4

5. Dead time for an ideal RC2-CR shaping
<MIP>
<MIP>/4
V. Re
SuperB Workshop, Frascati, April 4, 2011 5

6. ENC estimate
Layer
CD [pF]
tp [ns]
ENC from RS [e rms]
ENC [e rms]
Channel width [mm]
Hit rate/strip [kHz]
Efficiency 1/(1+N)
11.2 25
220
680
1450
2060
0.890 1
26.7 50
650
1190
3010
268
0.969
100
460
930
3770
0.940 2
31.2
830
1400
3300
179
0.979 3
45.8
1480
2130
4120
52.5
0.994 4
52.6
1000
340
820
11370
21.9
0.950 5
67.5
500
1010
13500
18.7
0.957
RC2CR shaping, ID=500 mA (current in the PA input device), L=200 nm, N-channel input device, analog dead time=2.4 tp
V. Re
SuperB Workshop, Frascati, April 4, 2011 6

7. ENC estimate
Layer
CD [pF]
tp [ns]
ENC from RS [e rms]
ENC [e rms]
Channel width [mm]
Hit rate/strip [kHz]
Efficiency 1/(1+N) 2
31.2 50
830
1400
3300
179
0.979
100
590
1080
4140
0.959
200
420
860
5110
0.921 3
45.8
1480
2130
4120
52.5
0.994
1050
1600
5180
0.988
740
1240
6510
0.975
400
520
980
8050
0.952
RC2CR shaping, ID=500 mA, L=200 nm, N-channel input device, analog dead time=2.4 tp
V. Re
SuperB Workshop, Frascati, April 4, 2011 7

8. ENC estimate
Layer
CD [pF]
tp [ns]
ENC from RS [e rms]
ENC [e rms]
Channel width [mm]
Hit rate/strip [kHz]
Efficiency 1/(1+N) 4
52.6
1000
340
820
11370
21.9
0.950
800
380
870
10730
0.960
500
490
9430
0.974 5
67.5
1010
13500
18.7
0.957
560
1080
12680
0.965
710
1250
11060
0.978
RC2CR shaping, ID=500 mA, L=200 nm, N-channel input device, analog dead time=2.4 tp
V. Re
SuperB Workshop, Frascati, April 4, 2011 8

9. Comments
From the noise standpoint, it would be obviously desirable to reduce the strip resistance as well as the detector capacitance (by increasing the strip readout pitch: what about the strip hit rate?)
According to these estimates, detection efficiency in a layer 0 with striplets is < 90% at full luminosity (with safety factor)
V. Re
SuperB Workshop, Frascati, April 4, 2011 9

10. Monolithic Active Pixel Sensors in the INMAPS process (CMOS 180 nm)
The deep P-well can be used to prevent parasitic charge collection by n-wells competing with the sensing electrode
The technology provides epitaxial layers 5 or 12 mm thick with a maximum resistivity of 50 Ω*cm
High resistivity epitaxial layers (1 kΩ*cm) 12 or 18 mm thick are also available.
Deep P-well combined with high resistivity epi-layer increases the charge collection efficiency. This makes it possible to use a simple nwell diode instead of a large DNW sensor, reducing the overall noise.

11. INMAPS CHANNEL READOUT CHAIN
Vbl=750 mV
Imir=20 nA
Cfb=5 fF
C1=160 fF
C2=25 fF
A preliminary design and layout of each block in the figure above has been carried out.
All the simulations have been performed keeping CD=40 fF.
Use of a mirror feedback configuration for C2 discharge instead of the transconductor in order to reduce the overall noise and threshold dispersion.
V. Re
SuperB Workshop, Frascati, April 4, 2011 11 11

12. INMAPS: SIMULATED PERFORMANCE AND PLANS
P=18 uW per pixel
Output waveform tp=230 ns
ENC=30 e (CD=40 fF)
Threshold dispersion=13e (at the shaper output)
Threshold dispersion=23e (including discriminator contribution)
15um
Charge sensitivity = 970 mV/fC
In the INMAPS technology, we plan to test a fast readout architecture (“hybrid-pixel-like”, as in APSEL MAPS) with pixel-level sparsification and time stamping, which seems to fit at best the high background rate of Layer0.
V. Re
SuperB Workshop, Frascati, April 4, 2011 12

13. ciao
3D integrated MAPS from the first 3D-IC MPW run: still waiting for 3D chips
In 2009, the Italian VIPIX collaboration submitted 3D active pixel devices in the first run of the 3DIC Consortium hosted by Fermilab.
In this run, we designed 3D MAPS with two layers (“tiers”) of the 130 nm CMOS process by Chartered Semiconductor, vertically integrated with the Tezzaron interconnection technology.
In January 2011, we received the first samples, before the interconnection (see talk by S. Bettarini). The 3D interconnection process by Tezzaron is scheduled this week.
V. Re
SuperB Workshop, Frascati, April 4, 2011 13
saluti

14. ciao
V. Re
SuperB Workshop, Frascati, April 4, 2011 14
saluti

15. VIPIX plans and designs
The second 3D-IC run:
VIPIX plans and designs
The VIPIX collaboration is at an advanced stage in the design work for a second MPW run in the 3D Tezzaron/Chartered process.
This second run will take place about 3 months after we get 3D devices from the first run, to allow enough time for testing
No change in 3D integration technology is foreseen for the second run (TSV drilled at Chartered)
The following devices will be included by VIPIX in the second run, targeting SuperB SVT specifications:
“test beam grade” MAPS : 100x128, 50 um pitch (~32 mm2 active area) with high rate sparsified readout architecture
a 3D readout chip for high resistivity pixel sensors (similar architecture) : 128x32, 50 um pitch (~10.3 mm2 active area)
V. Re
SuperB Workshop, Frascati, April 4, 2011 15

16. Main front-end design features
The analog section of the 3D readout chip for high resistivity pixels
Main front-end design features
CD [fF]
(detector+bonding)
150
CF [fF] 32
C1 [fF] 25
C2 [fF] 12
Preamplifier Input Device [m/m]
18/0.25
Analog Supply [V]
(AVDD)
1.5
Analog Power Dissipation [W/pixel] 10
Peaking Time [ns]
(Qinject =16000 e-)
260
Charge sensitivity
[mV/fC] 48
ENC
[e- rms]
130
Threshold dispersion
560 (before corr.)
65 (after corr.)
Block diagram of the analog front-end circuit for high resistivity pixel sensor
V. Re
SuperB Workshop, Frascati, April 4, 2011 16

17. Analog front-end for the ApselVI 3D MAPS chip (v2)CF C1 C2
VTHR
VREF
A(s)
Design features and simulation results
W/L=32/0.25, ID,PA=16 mA
Total power dissipation=33 μW
CD=300 fF
320 ns peaking time
Charge sensitivity: 850 mV/fC
ENC: 34 electrons
Threshold dispersion: 103 electrons
V. Re
SuperB Workshop, Frascati, April 4, 2011 17

18. Voltage drop on analog power/ground lines: compensation
May be an issue with large matrices of relatively current-hungry detectors (e.g. DNW MAPS): front-end features can degrade due to voltage drop on the power and ground lines causing changes in some pixel current sources – shaper input branch and transconductor
This problem can be overcome if currents are correctly mirrored in pixel cells
V. Re
SuperB Workshop, Frascati, April 4, 2011 18

19. SuperB SVT and the AIDA project
February 1st, 2011 was the kick-off date for the AIDA project, a EU-funded FP7 program addressing infrastructures for detector development for future particle physics experiments (
In AIDA, WorkPackage3 aims to establish a network of groups from European universities and high energy physics research institutes working collaboratively on 3D integration technology for thin pixel sensors with complex pixel-level functionality, with small pixel size and without dead regions (as needed by SVT Layer0).
A major goal of AIDA WP3 is to build a demonstrator based on 3D integration. WP3 plans to follow a “via last ” approach to 3D integration to build a 2-layer device in heterogeneous technologies (e.g., high-resistivity pixel sensors and CMOS readout chips).
We are organizing a 1-day workshop in Bergamo, Italy, on May 23rd, The goal of this workshop is to begin a discussion with industries and research institutes which may provide 3D technology to the AIDA WP3 network
V. Re

20. AIDA WP3 and SVT Layer0
AIDA WP3 will pursue an alternative approach to 3D integration with respect to the 3D-IC consortium. This opens up new opportunities and technical solutions for a Layer0 based on 3D integrated pixels.
3D-IC consortium:
3D integrated circuits with the Tezzaron process
“via first” process, where TSVs are drilled at the foundry in the early stages of CMOS wafers processing. Very high density interconnections (< 10 mm) are possible.
AIDA WP3:
Advanced pixel sensors based on 3D integration of 2 layers in heterogeneous technologies
“via last” process, 4-side buttable device with low density interconnections in the device periphery. 20

21. 65 nm CMOS MAPS
The demand for higher in-pixel functionalities along with the reduction of pixel cell size drives the interest of the designers community towards sub-100 nm CMOS processes in the design of mixed signal front-end electronics
We fabricated a prototype chip with active pixel sensors (same architecture as APSEL chips) and fast front-end circuits in the Low Power 65 nm CMOS process by IBM (10LPE/10RFE)
Tests have just started, preliminary results are available
MAPS analog channel
Fast front-end
V. Re
SuperB Workshop, Frascati, April 4, 2011 21

22. Conclusions
R&D on advanced pixels is in progress, various technologies are being explored
Concerning SVT strips, real work on chip design has to start soon (two different chips are needed)
V. Re
SuperB Workshop, Frascati, April 4, 2011 22

23. Backup slides
V. Re

24. Via First Approach
Through silicon Via formation is done either before or after CMOS devices (Front End of Line) processing
Form vias before transistors
IBM, NEC,
Elpida, OKI,
Tohoku, DALSA….
Tezzaron, Ziptronix
Chartered, TSMC,
RPI, IMEC……..
Form transistors before vias
TWEPP-08

25. Via Last Approach
Via last approach occurs after wafer fabrication and either before or after wafer bonding
Zycube, IZM,
Infineon, ASET…
Samsung, IBM,
MIT LL, RTI,
RPI….
Notes: Vias take space away from all metal layers. The assembly process
is streamlined if you don’t use a carrier wafer.
TWEPP-08

26. Bonding Choices Electrical and Mechanical Bonds Fermilab experience
(MIT LL)
(RTI)
(Tezzaron)
(Ziptronix)
TWEPP-08

27. TEMPERATURE VARIATION
The channel readout has been simulated in the temperature range between 0°C and 80°C.
Gain temperature coefficient = -420 uV/(°C fC)
Charge sensitivity = 970 mV/fC
Taking into account a temperature variation of 10°C for each 10 cm module, considering a 1 cm chip width, we have a variation of 1°C per chip, that corresponds to:
Charge sensitivity variation= [-0.42 mV/(°C fC)] / [970 mV/fC] =
= -0.04%
Analogous considerations can be done regarding the baseline variation depending on the temperature:
Baseline temperature coefficient = 0.56 mV/°C
VoutSHAPER=121 Qinj=800 electrons
Considering a 1°C/chip variation:
σ2VblΔT=[0.56 mV/121 mV]*800e=4 electrons due to a 1°C variation
σ2Vbl=23 electrons due to mismatch variations (Discriminator output)
[σ2VblΔT/σ2Vbl]2=3%

28. Vertically integrated MAPS in the second 3D-IC run: APSEL
Beam axis
1.6 mm
0.5 mm
0.25 mm
~ 38 Pad – pitch 130 mm
Piste data line di 2 sottomatrici
0.16 mm
6.4 mm
Submatrix 1: 128x50
128x100 pixel matrix
50 mm pitch
Active area=32mm2
Readout=8mm2
Area~x2x area from FE32x128
5 mm
5.56 mm
~ 38 Pad – pitch 130 mm
~ 38 Pad – pitch 130 mm
Submatrix 2: 128x50
Piste data line di 2 sottomatrici
0.16 mm
0.120 mm cut line
8.99 mm
V. Re
SuperB Workshop, Frascati, April 4, 2011 28

29. An example of how 3D integration is exploited in the second run: in-pixel logic with time-stamp latch for a time-ordered readout
No Macropixel
Timestamp (TS) is broadcast to pixels & pixel latches the current TS when is fired.
Matrix readout is timestamp ordered
A readout TS enters the pixel, and a HIT-OR-OUT is generated for columns with hits associated to that TS.
A column is read only if HIT-OR-OUT=1
DATA-OUT (1 bit) is generated for pixels in the active column with hits associated to that TS
TSComp.
DATA-OUT
HIT-OR-OUT
This more complex in pixel logic will be implemented with 3D integration without reducing the pixel collection efficiency even improving the readout performance (readout could be data push or triggered)
VHDL simulation of the data push chip (100MHz/cm2 input hit rate)
Readout Effi > MHz clock with timestamp of 200 ns.
V. Re

30. Cell layout
In this prototype the digital section is kept to a minimum (latch, OR gate, tri- state buffer). It is planned to include sparsification and time- stamping logic at the pixel level in more advanced versions (room for this already available)
40 um
n-well PMOSFETs
(area ≈ 50 µm2)
Sensor
(area ≈ 360 µm2)
V. Re
SuperB Workshop, Frascati, April 4, 2011 30

31. APSEL65 DNW MAPS
Classical signal processing chain for capacitive detector
The analog processor includes a charge sensitive amplifier, a shaping stage and a threshold discriminator  binary readout
V. Re