1. Design Rules

2. 3D Perspective
Polysilicon
Aluminum

3. Design Rules Interface between designer and process engineer
Guidelines for constructing process masks
Unit dimension: Minimum line width
scalable design rules: lambda parameter
absolute dimensions (micron rules)

4. CMOS Process Layers Layer Polysilicon Metal1 Metal2 Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color
Representation
Yellow
Green
Red
Blue
Magenta
Black
Select (p+,n+)

5. Layers in 0.25 mm CMOS process

6. Intra-Layer Design Rules4
Metal2 3

7. Transistor Layout

8. Vias and Contacts

9. Select Layer

10. CMOS Inverter Layout

11. Layout Editor

12. Design Rule Checker
poly_not_fet to all_diff minimum spacing = 0.14 um.

13. Sticks Diagram 1 V 3 In Out GND Dimensionless layout entities
Stick diagram of inverter
Dimensionless layout entities
Only topology is important
Final layout generated by “compaction” program