1. Pipelined Architectures for High-Speed and Area-Efficient Viterbi Decoders
Chen, Chao-Nan Chu, Hsi-Cheng

2. Convolutional code
Viterbi decoder
In-place path metric updating
Inserting pipeline levels into ACS

3. Fig.1 A simple rate ½, v = 3 convolutional encoder
Convolutional Codes
Convolutional encoders map information streams into a long code sequence.
k = 1 bit input blocks produce n = 2 code symbols each.
The code rate k/n expresses the information per coded bit and the constraint length v defines the encoder memory order.
This encoder has 2(v – 1) = 4 states.
1st code symbol
input
output
2nd code symbol
Fig.1 A simple rate ½, v = 3 convolutional encoder

4. Viterbi Algorithm (VA)
The most commonly employed decoding technique that can be implemented using either software or digital hardware.
VA uses the trellis diagram (Fig.2) and can theoretically perform maximum likelihood decoding.
It finds the most likely path by means of suitable distance metric between the received sequence and all the trellis paths. 00 00 00 00 00 00 11 11 11 11 11
input bit 0 01 10 10 10 10
input bit 1 11 11 11 10 00 00 00 01 01 01 01 01 01 01 11 10 10 10
Fig.2 Trellis diagram representation of the encoder of Fig.1

5. Fig.3 Basic computation units in Viterbi decoder
BMU: BM are computed from introduced input data
ACSU: PMs of all states are updated according to equation (1)
SMU: The stored decisions are employed in the SMU to build a unique decoded output
PM[i](t+1) = min ( PM[k](t) + BM([k][i])(t) ) (1)
PM[k](t) : Path metric corresponding to state k at instant t
BM([k][i])(t): Branch metric of the transtion from state k at t to state i at t+1
all possible
Branch Metric
Unit
(BMU)
ACS
Unit
Survior-Path
Memory Unit
(SMU)
Input
Output
Fig.3 Basic computation units in Viterbi decoder

6. In-place Path Metric Updating
State i
i+2v-1 2i
2i+1
Overwrites previous metric of state i
Efficiently save half memory size
Overwrites previous metric of state i+2v-1
Fig. 3. Partial trellis diagram or butterfly for
in-place computation of updated path metrics.
State
State
State
State
State
State 1 1 1 2 4 1 2 2 2 4 1 2 3 3 3 6 5 3 4 4 4 1 2 4 5 5 5 3 6 5 6 6 6 5 3 6 7 7 7 7 7 7
(a)
(b)
Fig. 4. Example for v=3: (a) butterflies in the traditional approach;
(b) states and butterfies during one full cycle of in-place computation

7. Figure 5. The diagram of BF unit
State i
i+32 2i
2i+1
Figure 5. The diagram of BF unit
Table 1. State arrangement and path metric updating for constraint length 7 (64 states)
Figure 6. A novel architecture for the Viterbi decoder
Table 2. Address scrambling of path metric memory for constraint length 7 (64 states)
Cycle 1 2 3 4 5 6 7
Iterarion
Address(DpRAM0-3)
Address(DpRAM4-7)
Iteration

8. Figure 5. The diagram of BF unit
State i
i+32 2i
2i+1
Figure 5. The diagram of BF unit
Table 1. State arrangement and path metric updating for constraint length 7 (64 states)
Figure 6. A novel architecture for the Viterbi decoder
Table 2. Address scrambling of path metric memory for constraint length 7 (64 states)
Cycle 1 2 3 4 5 6 7
Iterarion
Address(DpRAM0-3)
Address(DpRAM4-7)
Iteration

9. Figure 5. The diagram of BF unit
State i
i+32 2i
2i+1
Figure 5. The diagram of BF unit
Table 1. State arrangement and path metric updating for constraint length 7 (64 states)
Figure 6. A novel architecture for the Viterbi decoder
Table 2. Address scrambling of path metric memory for constraint length 7 (64 states)
Cycle 1 2 3 4 5 6 7
Iterarion
Address(DpRAM0-3)
Address(DpRAM4-7)
Iteration

10. Figure 5. The diagram of BF unit
State i
i+32 2i
2i+1
Figure 5. The diagram of BF unit
Table 1. State arrangement and path metric updating for constraint length 7 (64 states)
Figure 6. A novel architecture for the Viterbi decoder
Table 2. Address scrambling of path metric memory for constraint length 7 (64 states)
Cycle 1 2 3 4 5 6 7
Iterarion
Address(DpRAM0-3)
Address(DpRAM4-7)
Iteration

11. Insert Pipeline Levels into ACS
Generally, the maximum number of ACS pipeline levels is only dependent on the ratio N/P (N: number of states ; P: number of ACS unit)
Table 3. The maximum pipelines levels for (N/P) from 1 to 64
N/P 1 2 4 8 16 32 64
ACS pipline levels 5 10 20 40
Figure 7. A simple example of inserting pipeline levels into ACS unit
PM[k](t) +
Comparator
BM[k][i](t)
Selector
PM[i](t+1)
PM[j](t) +
BM[j][i](t)

12. Conclusion
Assuming pipeline levels are equally distributed into ACS, the decoding speed is LP/N ≈ 5/8 of a state-parallel ACS instead of P/N.
The maximum possible area-saving can be obtained by selecting a large enough ratio N/P
A favorable solution for applications, where area-saving and hence power, is the most crucial while moderate decoding speed degradation is allowed.