1. Chapter 1 Number Systems, Number Representations, and Codes

2. Table 1 Counting Sequence for Different Radices
1.1 Number Systems
Decimal
r=2
r=4
r=8 1 2 10 3 11 4
100 5
101 6
110 12 7
111 13 8
1000 20
Table 1 Counting Sequence for Different Radices

3. 1.1.1 Binary Number System
The radix is 2 in the binary number system; therefore, only two digits are used: 0 and 1.
The weight assigned to each position of a binary number is as follows:
2n-1 2n m
= (1 × 23)+(0 × 22) +(1 × 21) +(1 × 20) (1 × 2-1) +(0 × 2-2) +(1 × 2-3) =

4. Table 2 Counting in Binary
A binary number is a group of n bits that can assume 2n different combinations of the n bits. The range for n bits is 0 to 2n -1.
Table 2 shows the weight associated with each of the four binary positions.
Decimal
Binary 8 4 2 1 23 22 21 20 3 5 6 7
Decimal
Binary 8 4 2 1 23 22 21 20 9 10 11 12 13 14 15
Table 2 Counting in Binary

5. Table 3 Counting in Octal
1.1.2 Octal Number System
The radix is 8 in the octal number system; therefore, eight digits are used, 0 through 7.
Decimal
Octal 64 8 1 82 81 80 2 3 4 5 6 7
Decimal
Octal 64 8 1 82 81 80 9
... 14 6 84 2 4
242 3
Table 3 Counting in Octal

6. Table 4 Binary-Coded Octal Numbers
Decimal
Octal
Binary-Coded Octal
000 1
001 2
010 3
011 4
100 5
101 6
110 7
111 8 10 9 11 12
... 20 24
145
267
413
Table 4 Binary-Coded Octal Numbers

7. Table 5 Binary-Coded Decimal Numbers
1.1.3 Decimal Number System
The radix is 10 in the decimal number system; therefore, ten digits are used, 0 through 9.
Decimal
Binary-Coded Octal
0000 1
0001 2
0010 3
0011 4
0100 5
0101 6
0110 7
0111 8
1000 9
1001 10
...
124
365
Binary-coded decimal
Each decimal digit can be encoded into a corresponding binary number; however, only ten decimal digits are valid.
Therefore, four binary digits are required to represent each decimal digit.
Table 5 Binary-Coded Decimal Numbers

8. Binary-coded hexadecimal
1.1.4 Hexadecimal Number System
The radix is 16 in the hexadecimal number system.
Decimal
Hexadecimal
Binary-Coded Octal
0000 1
0001 2
0010 3
0011 4
0100 5
0101 6
0110 7
0111 8
1000 9
1001 10 A
1010 11 B
1011 12 C
1100 13 D
1101 14 E
1110 15 F
1111
Binary-coded hexadecimal
All 24 values of the four binary bits are used to represent the 16 hexadecimal digits.
Each hexadecimal digit corresponds to a 4-bit binary number as shown in Table 6.
Table 6 BCH Numbers

9. 1.1.5 Arithmetic Operations
Radix 2 Addition
and carry 1 to the next column
Example:
carries

10. Radix 2 Subtraction and borrow 1 from the next column Example:
(indicates
a borrow
From the
3rd column)
borrows

11. Radix 2 Multiplication Multiply: 13 x11(10) multiplicand multiplier
first partial product
second partial product
sum of first two partial products
third partial product
sum after adding third partial product
fourth partial product
final product (sum after adding fourth partial prodoct)

12. Radix 2 Division
The quotient is 1101 with a remainder
of 10.

13. 1.1.6 Conversion Between Radices
Convert from radix ri to any other radix rj
1259 =(1×92) +(2×91)+(5×90)=10410
Convert to radix 7.
104 ÷7 = quotient = 14, remainder=6 (6 is the low-order digit)
14 ÷ 7 = quotient = 2, remainder=0
2 ÷ 7 = quotient = 0, remainder=2
Verify the answer
1259 = 2067 = (2×72) + (0×71) + (6×70) = 10410

14. Octal to hexadecimal
To convert from octal to hexadecimal, the octal number is first converted to BCO then partitioned into 4-bit segments to form binary-coded hexadecimal(BCH).
The BCH notation is then easily changed to hexadecimal, as shown below. 7 6 3 5 . 4 1 F 9 D 8

15. 1.2 Number Representations
The leftmost(high-order) digit is usually reserved for the sign of the number.
A = (an-1an-2an-3...a2a1a0)r
where digit an-1 has the following value:
0 if A≥0
r-1 if A<0
A =

16. 1.2.1 Sign Magnitude
A = (0an-2an a1a0)r
A'= [(r -1)an-2an a1a0]r
There are two problems with sign-magnitude representation.
First, there are two representations for the number 0; specifically +0 and -0; ideally there should be a unique representation for the number 0.
Second, when adding two numbers of opposite signs, the magnitudes of the numbers must be compared to determine the sign of the result.

17. Examples 0 0 0 0 0 1 0 0 +4 1 0 0 0 0 1 0 0 −4 Magnitude Sign −4
Magnitude
Sign
−13.625
Radix 10
−743

18. 1.2.2 Diminished-Radix Complement
A = (0an-2an a1a0)r
A'= [(r−1)an-2'an-3' ... a1'a0']r (ai' = (r − 1) −ai )
Positive integers: 0 to 2n−1−1
Negative integers: 0 to −(2n−1−1)
−6010

19. Number Representation Diminished-radix complement
A = (0an-2an a1a0)r
(A')+1= {[(r−1)an-2'an-3' ... a1'a0']+1}r
Number Representation
Positive Numbers
Negative Numbers
Sign magnitude
0an-2an a1a0)r
(r -1)an-2an a1a0
Diminished-radix complement
(r− 1)an-2'an-3' ... a1'a0'
Radix complement
(r− 1)an-2'an-3' ... a1'a0'+1
Table 8 Number Representations for Positive and Negative Integers of the Same Absolute Value for Radix r

20. 1.2.4 Arithmetic Operations
Binary Addition
Overflow
A = an-1an-2an a1a0
B = bn-1bn-2bn b1b0
Overflow = (an-1• bn-1 • sn-1') + (an-1' • bn-1' • sn-1)
Overflow = cn-1⊕cn-2=(cn-1• cn-2') +(cn-1'• cn-2)
“•” -----logical AND “+”-----logical OR
“⊕”-----exclusive-OR
Cn-1 and Cn-2 are the carry bits out of positions n − 1 and n − 2, respectively.

21. Binary subtraction A = Minuend − ) B = Subtrahend Difference
Difference = A − B
= A − rn + rn − B
= A − rn + (rn − B)
= A − rn + (B' +1)

22. Binary multiplication
A = an-1an-2an a1a0
B = bn-1bn-2bn b1b0
Product of A×B =p2n-1p2n-2p2n p1 p0
A = Multiplicand (n bits)
×) B = Multiplier (n bits)
P = Product (2n bits)

23. Example
(+7)
×) (+5)
(+35)

24. Binary division Dividend = ( Quotient × Divisor ) + Remainder
A = a2n-1a2n anan a1a (Dividend)
B = bn-1bn-2bn b1b (Divisor)
Q = qn-1qn-2...q1q0
R = rn-1rn r1r0
qn-1 = a2n-1 ⊕ bn-1

25. Table 9 Examples of Binary Codes for Decimal Digits
1.3.1 Binary Weighted and Nonweighted Codes
Table 9 Examples of Binary Codes for Decimal Digits

26. 1.3.2 Binary-to-BCD Conversion
BCD digits in the range 0-4 do not require an adjustment after being shifted left, because the shifted number will be in the range 0-8, which can be contained in a 4-bit BCD digit.
If the number to be shifted is in the range 5-9, then an adjustment will be required after the left shift, because the shifted number will be in the range 10-18, which requires two BCD digits.

27. Figure 1 Example of binary-to-BCD conversion

28. 1.3.3 BCD-to-Binary Conversion
In general, if the high-order bit in any decade is a 1 after the shift-right operation, then a value of 3 must be subtracted from the decade.

30. Table 10 Binary 8421 Code and the Gray Code
←y4 is reflected
← y3 and y4 are reflected
← y2, y3 and y4 are reflected
Table 10 Binary 8421 Code and the Gray Code

31. Binary-to-Gray code conversion
Where b0 and g0 are the low-order bits of the binary and Gray codes, respectively.
The ith Gray code bit gi can be obtained from the corresponding binary code word by the following algorithm:
gn-1 = bn-1
gi = bi ⊕ bi+1

32. Gray-to-binary code conversion
Where b0 and g0 are the low-order bits of the binary and Gray codes, respectively.
bn-1 = gn-1
bi = bi+1 ⊕ g
Example
g3g2g1g0 = 1001
b3 = g =1
b2 = b3 ⊕ g2 = 1 ⊕ 0 = 1
b1 = b2 ⊕ g1 = 1 ⊕ 0 = 1
b0 = b1 ⊕ g0 = 1 ⊕ 1 = 0

33. 1.4 Error Detection and Correction Code
1.4.1 Parity
An extra bit can be added to a message to make the overall parity of the code word either odd or even.
The number of 1s in the code word −message bits plus parity bit.
Parity bit(even) = m3 ⊕ m2 ⊕ m1 ⊕ m0

34. Table 11 Parity Bit Generation

35. When a word is to be transmitted, the parity bit is generated (PG) and the nine bits are transmitted along the 9-bit parallel bus.
At the receiving end, the parity of the word is checked (PC) and the parity bit is removed.
The parity generator and parity checker are both implemented using modulo-2 addition.

36. Code word X =x1,x2, ………, xm, xm+1, … , xn
1.4.2 Hamming Code
The Hamming code can be considered as an extension of the parity code presented in the previous section, because multiple parity bits provide parity for subsets of the message bits.
Code word X =x1,x2, ………, xm, xm+1, … , xn

37. Figure 2 Possible track format for a disk drive
1.4.3 Cyclic Redundancy Check Code
A class of codes has been developed specifically for serial data transfer called cyclic redundancy check (CRC) codes.
Figure 2 Possible track format for a disk drive

38. Figure 3 One frame of the synchronous data link control format.
The first field is the flag field, which is a delimiter indicating the beginning of block.
This is followed by an address field, which is decoded by all receivers, then a control field, indicating frame number, last frame, and other control information.
The text field contains n bits of serial data followed by a 16-bit CRC character.
Figure 3 One frame of the synchronous data link control format.

39. Figure 4 Checksum generated for a 4-byte message.
The checksum is the sum derived from the application of an algorithm that is calculated before and after transmission to ensure that the data is free from errors.
Figure 4 Checksum generated for a 4-byte message.

40. Table 12 Two-out-of-Five Code for the Decimal Digits
The two-out-of-five code is 5-bit nonweighted code that is characterized by having exactly two 1s and three 0s in any code word.
Table 12 Two-out-of-Five Code for the Decimal Digits

41. 1.4.6 Horizontal and Vertical Parity Check
An alternative method to Hamming code for smaller memories − which has less redundancy − is a technique using horizontal and vertical parity.
Horizontal parity utilizes an odd parity bit for each word in memory.
Vertical parity is the modulo-2 addition of identical bit positions of each word in a block of memory.

42. Figure 5 Ten-word memory to illustrate single-error detection and correction using horizontal and vertical parity

43. Example
Assume that word four has an error in bit position four such that word four changes from to , which is incorrect for odd parity.
As another example, assume that word seven has an error in bit position two such that word seven changes from to , which is incorrect for odd parity.

44. 1.5 Serial Data Transmission
There are two basic types of serial communication: synchronous and asynchronous.
In synchronous communication, information is transferred using a self-clocking scheme; that is, the clock is synchronized to the data, which determines the rate of transfer.
In asynchronous communication, the timing occurs for each character. The communications line for asynchronous serial data transfer is in an idle state (a logic 1 level) when characters are not being transmitted.

45. Figure 6 Asynchronous serial data transfer for the ASCII character W.