1. Principles of Computers 16th Lecture
Pavel Ježek, Ph.D.

2. Examples of CPU Architectures
CPU name
Data width
Logical address width
Current instruction
register(s)
Physical address width
Special mode
8-bit
6502
MOS 6502
8-bit data
16-bit PC
(64 kB)
x86-16
x86
Intel 8088
bit
CS:IP
20-bit
(1 MB)
Intel 8086
16-bit data
Intel 80286
24-bit
(16 MB)
protected 16
(+ real) mode
32-bit
IA-32
INTEL32
Intel 80386
32-bit data
EIP
(4 GB)
protected 32
mode
Intel Pentium Pro
64-bit data
36-bit
(64 GB)
PAE
64-bit
x64
x86-64
AMD64
INTEL64
EM64T
AMD Opteron
(Intel Pentium 4)
RIP
40-bit
(1 TB)
long mode
2015 current
(e.g. Core i7)
AMD: 48b → 256 TB
Intel: 46b → 64 TB
32-bit ARM
64-bit ARM
32b MIPS
MIPS64
PowerPC (PPC)
32b Motorola (68k)

3. Aligned and Misaligned Accesses
16b word
16b word
16b word
16b word
16b word
16b word 1 2 3 4 5
addr. space of “16-bit memory”
translation:
WordAddr := ByteAddr div 2 1 2 3 4 5 6 7 8 9 A B
CPU addr. space (always byte addr)
byte
translation:
WordAddr := ByteAddr div 4 1 2
addr. space of “32-bit memory”
32b word
32b word
32b word
translation:
WordAddr := ByteAddr div 8 1
“64-bit mem”
64b word
64b word

4. Aligning a 2 Byte Value 1 2 3 4 5 1 2 3 4 5 6 7 8 9 A B 1 2 1
16b word
16b word
16b word
16b word
16b word
16b word 1 2 3 4 5
addr. space of “16-bit memory”
translation:
WordAddr := ByteAddr div 2 1 2 3 4 5 6 7 8 9 A B
CPU addr. space (always byte addr)
byte
translation:
WordAddr := ByteAddr div 4 1 2
addr. space of “32-bit memory”
32b word
32b word
32b word
translation:
WordAddr := ByteAddr div 8 1
“64-bit mem”
64b word
64b word

5. Aligning a 2 Byte Value 1 2 3 4 5 1 2 3 4 5 6 7 8 9 A B 1 2 1
16b word
16b word
16b word
16b word
16b word
16b word 1 2 3 4 5
addr. space of “16-bit memory”
valid alignments for 2 byte access on memory bus with 2 byte (16 bit) data bus ↓
operation size = data bus size
valid alignments = alignment on 2 byte boundary
translation:
WordAddr := ByteAddr div 2 1 2 3 4 5 6 7 8 9 A B
CPU addr. space (always byte addr)
byte
translation:
WordAddr := ByteAddr div 4 1 2
addr. space of “32-bit memory”
32b word
32b word
32b word
translation:
WordAddr := ByteAddr div 8 1
“64-bit mem”
64b word
64b word

6. Aligning a 4 Byte Value 1 2 3 4 5 1 2 3 4 5 6 7 8 9 A B 1 2 1
16b word
16b word
16b word
16b word
16b word
16b word 1 2 3 4 5
addr. space of “16-bit memory”
translation:
WordAddr := ByteAddr div 2 1 2 3 4 5 6 7 8 9 A B
CPU addr. space (always byte addr)
byte
translation:
WordAddr := ByteAddr div 4 1 2
addr. space of “32-bit memory”
32b word
32b word
32b word
translation:
WordAddr := ByteAddr div 8 1
“64-bit mem”
64b word
64b word

7. Aligning a 4 Byte Value 1 2 3 4 5 1 2 3 4 5 6 7 8 9 A B 1 2 1
16b word
16b word
16b word
16b word
16b word
16b word 1 2 3 4 5
addr. space of “16-bit memory”
translation:
WordAddr := ByteAddr div 2 1 2 3 4 5 6 7 8 9 A B
CPU addr. space (always byte addr)
byte
valid alignments for 4 byte access on memory bus with 4 byte (32 bit) data bus ↓
operation size = data bus size
valid alignments = alignment on 4 byte boundary
translation:
WordAddr := ByteAddr div 4 1 2
addr. space of “32-bit memory”
32b word
32b word
32b word
translation:
WordAddr := ByteAddr div 8 1
“64-bit mem”
64b word
64b word