1. Predicting Performance Impact of DVFS for Realistic Memory Systems Rustam Miftakhutdinov Eiman Ebrahimi Yale N. Patt

2. V f Dynamic Voltage/Frequency Scaling 2 Image source: intel.com

3. f opt Impact of Frequency Scaling frequency time power energy 3

4. fofo Impact of Frequency Scaling power time 4 frequency

5. f opt Prediction Overview 5 instructions frequency energy per instruction 100K200K300K0 fofo freq. time fofo freq. power fofo fofo freq.f opt energy our work ×

6. Outline Intro to performance prediction Why realistic memory systems? Variable memory latency Prefetching 6 ✓

7. V f Why Realistic Memory System? 7

8. Prior Work Stall time Leading loads (2010) S. Eyerman et al. G. Keramidas et al. B. Rountree Evaluated with constant access latency memory system 8

9. Energy Savings Gmean of relative savings for 13 memory-intensive SPEC 2006 benchmarks. Baseline: most energy-efficient static frequency for SPEC 2006 * 9

10. Energy Savings 10 Gmean of relative savings for 13 memory-intensive SPEC 2006 benchmarks. Baseline: most energy-efficient static frequency for SPEC 2006 *

11. Outline 11 Intro to performance prediction Why realistic memory systems? Variable memory latency Prefetching ✓ ✓

12. Execution Example chip activity memory requests 12 A B C D E 1234 time

13. T = T memory + T compute 13 independent of frequency proportional to cycle time

14. toto Linear Model execution time T cycle time t T memory T compute 14 0

15. Measuring T memory chip activity memory requests time 15

16. Measuring T memory chip activity memory requests time 16

17. Causes of Request Dependences 17 next Pointer Chasing instruction window miss Finite Chip Resources

18. Measuring T memory chip activity memory requests time 18

19. Critical Path Algorithm at T start 1. record T start and T memory T end T start time T memory 19 at T end 2. compute path = T memory (T start ) + (T end - T start ) old critical pathrequest latency 3. set T memory = max(T memory, path) new T memory (length of critical path)

20. toto Linear Model execution time T cycle time t T memory T compute 20 0

21. Linear Model 21 toto execution time T cycle time t T memory T compute 0 toto cycle time TmTm time fofo freq. time fofo freq. power fofo freq.f opt energy ×

22. Critical Path: Variable Access Latency chip activity memory requests time 22 Leading Loads: Constant Access Latency time chip activity memory requests

23. toto Leading Loads execution time T cycle time t T memory T compute 23 0 leading loads

24. Leading Loads 24 toto execution time T cycle time t T memory T compute 0 leading loads toto cycle time TmTm time fofo freq. time fofo freq. power fofo freq.f opt energy ×

25. Energy Savings 25 Gmean of relative savings for 13 memory-intensive SPEC 2006 benchmarks. Baseline: most energy-efficient static frequency for SPEC 2006 *

26. Outline 26 Intro to performance prediction Why realistic memory systems? Variable memory latency Prefetching ✓ ✓ ✓

27. chip activity memory requests time Prefetcher OFF Prefetcher ON chip activity memory requests time Prefetcher ON Frequency +200 MHz chip activity memory requests time chip activity memory requests time Prefetcher ON Frequency +500 MHz Streaming Workload 27

28. Limited Bandwidth Model execution time T cycle time t T demand T compute T memory min t crossover 28 0

29. Energy Savings 29 Gmean of relative savings for 13 memory-intensive SPEC 2006 benchmarks. Baseline: most energy-efficient static frequency for SPEC 2006 *

30. Recap 30 Intro to performance prediction Why realistic memory systems? Variable memory latency Prefetching ✓ ✓ ✓ ✓

31. Final Thought Performance predictors need realistic evaluation 31