1. 6-bit 500 MHz flash A/D converter with new design techniques
C.W. Hsu and T.H. Kuo, ” 6-bit 500MHz flash A/D converter with new design techniques,” IEEE Proceedings Devices and Systems Circuits , Page(s) , Oct
Postgraduate : Ting-Yao Hsu

2. Outline Proposed ADC Architecture
New autozeroing with interpolation technique
Negative impedance compensation technique
Measurement results
Conclusion

3. Proposed ADC Architecture
Fig.1. Architecture of proposed ADC

4. New autozeroing with interpolation technique
Fig.2. Simple autozeroing comparator

5. New autozeroing with interpolation technique
Fig.3. Input stage of the conventional autozeroing technique

6. New autozeroing with interpolation technique
Fig.4. Input stage of NAI

7. Negative impedance compensation technique
Fig.5. Interpolation circuit diagram with NIC

8. Negative impedance compensation technique
Fig.6. Model diagram of NIC analysis

9. Negative impedance compensation technique
Fig.7. NIC circuit diagram

10. Fig.8. DNL and INL for the ADC at 500 Msample/s
Measurement results
Fig.8. DNL and INL for the ADC at 500 Msample/s

11. Measurement results

12. Conclusion
NAI solves the problems of the autozeroing with interpolation technique.
NIC can improve the ADC speed and maintain the desired interpolation effect.