1. Understanding Analog Performance Specifications

2. Agenda ADC Operation ADC Performance Specifications IDAC Operation
IDAC Performance Specifications
System-Level Performance Measurement
System-Level Error Compensation

3. ADC Operation

4. What is an ADC? ADC is an acronym for analog-to-digital converter
An ADC takes an analog voltage at its input and produces a digital number representing that voltage at its output

5. Output vs. Input
The output of an ADC is different from the input in two distinct ways
The input signal to the ADC is a continuous voltage, while the ADC output has been quantized to discrete steps that are represented as digital codes
The input signal is continuous in time, while the output is a series of discrete-time points
The output of an ADC is an approximation of the analog input. The accuracy of this approximation depends both on the analog precision of the ADC and the speed at which it can sample the input.

6. ADC: Input Range
An ADC’s input range is defined by the reference voltage (VREF) provided to the ADC
The power supplies to the ADC are also important in determining the absolute input voltage
In most ADC architectures, input voltages outside the supply rails cannot be measured and may cause damage to the device
The reference voltage defines one, sometimes both end points of the transfer function, depending on the type of ADC.
Silicon Labs does sell one MCU family (the C8051F04x) which incorporates a high-voltage difference amplifier in front of the ADC. The HVDA can accept absolute voltage inputs between +/-60 volts without damage.

7. ADC: Single-Ended
A “single-ended” ADC is one where a single input voltage is measured with respect to ground (AIN – GND)
Most single-ended ADCs have an input range from 0V to VREF
Common Problem: Input circuitry’s maximum output higher than VREF
If the ADC input voltage is above VREF, but below the supply voltage for the ADC, the device will not be damaged, but the ADC output will max out at full-scale.

8. ADC: Single-Ended Supply Measurement
One example of a single-ended voltage measurement is monitoring the supply to the system—the supply is divided down to within the input range of the ADC using a resistive divider
An amplifier circuit designed to attenuate the ADC input could also be used

9. ADC: Single-Ended: Setup
To initialize the ADC, the following registers have to be modified:
ADC0CN: ADC0 control register
REF0CN: To enable on-chip VREF and buffer
AMX0P and AMX0N: To select positive and negative input (in case of single-ended, AMX0N is set to GND)
ADC0CF: To set the SAR clock and the ADC0H:L justification
Remember to set the port pins being used by the ADC in the Port Initialization.

10. ADC: Single-Ended: Example Setup
ADC0CN = 0x02; // ADC0 disabled, normal tracking,
// conversion triggered on TMR2 overflow
REF0CN = 0x03; // Enable on-chip VREF and buffer
AMX0P = 0x01; // ADC0 positive input = P1.1
AMX0N = 0x1F; // ADC0 negative input = GND
// i.e., single ended mode
ADC0CF = ((SYSCLK/ )-1)<<3; // Set SAR clock to 3MHz
ADC0CF &= ~0x04; // Right-justify results
AD0EN = 1; // Enable ADC0

11. ADC: Differential
For a differential ADC, the difference in voltage between two pins is measured (AIN+ - AIN-)
The input range of a differential converter is –VREF to +VREF, or twice the range of a single-ended converter
Common Problem: Input circuitry designed to go below ground when supply to ADC is only positive

12. ADC: Differential
A “negative” differential measurement does not require a negative input voltage
If the difference between AIN+ and AIN- is negative, a negative output will be produced
If AIN+ = 1 V and AIN- = 2 V, the input to the ADC is
(AIN+ - AIN-) = (1 V – 2 V) = -1 V

13. ADC: Differential
The “Common Mode” of a differential measurement is: (AIN+ + AIN-) / 2
The common mode of the previous example would be
(AIN+ + AIN-) / 2 = (1 V + 2 V) / 2 = 1.5 V
The mid-point of the ADC output for a differential input is zero

14. ADC: Differential Bridge Measurement
An example of a differential input signal is a bridge measurement (such as a load cell)
The voltage of interest is the difference across the bridge
A bridge circuit is made up of resistors, some of which vary with change in a physical parameter. In a load cell for example, the variable elements are sensitive to pressure. When these elements change, the output of the resistive dividers also change.

15. ADC: Output Coding
The output code range of an ADC is 2N, where N is the number of bits in the output word
The digital output from an ADC represents the voltage present at the input, as a fraction of the reference voltage. With a single-ended converter whose input range is 0 V to VREF
Output = (VIN / VREF) x 2N; N = number of bits in output word
To calculate the input voltage from the output code
VIN = VREF x (Output / 2N); N = number of bits in output word
The term “LSB” is commonly used to refer to the amount of input voltage required to produce a single-code change at the output
One LSB = Input Voltage Range / Output Code Range
Example: For a single-ended 10-bit SAR using a 2.5 V reference, one LSB = (VREF / 210) = (2.5 V / 1024) = 2.44 mV
We are going to use the Output equation a number of times later in this section. The Output equation might also have to be used in programs that use the ADC. Pay special attention to this equation. Note: Since 2N is greater than Output, the result of the division (Output/2N) will always be zero. Make sure that you perform the multiplication before the division.
The size of an LSB is derived from the “Vin” equation. By setting the output to a value of 1, Vin becomes the LSB size.

16. ADC: Unipolar Output Coding
Unipolar output coding is used when the input signal to the ADC is positive
For a single-ended converter, output coding is normally unipolar
Unsigned binary encoding is used to represent unipolar output
Input Voltage
Output Code (10-bit)
>= VREF
1023 (0x03FF)*
VREF – 1 LSB
1023 (0x03FF)
½ VREF
512 (0x0200)
¼ VREF
256 (0x0100)
0 V
0 (0x0000)
* Output of ADC is saturated
Note that voltages above VREF will saturate the output at full scale.

17. ADC: Bipolar Output Coding
Bipolar output coding is used when the input to the converter can be positive or negative, as with a differential converter
For a differential converter, the input range is doubled, which also doubles the size of the LSB
2’s-complement binary encoding is typically used to represent bipolar output
Input Voltage
Output Code
(10-bit, sign extended)
>= VREF
511 (0x01FF)*
VREF – 1 LSB
511 (0x01FF)
½ VREF
256 (0x0100)
0 V
0 (0x0000)
- ½ VREF
-256 (0xFF00)
-VREF
-512 (0xFE00)
< -VREF
-512 (0xFE00)*
*Output of ADC is saturated
Voltages above or below the limits will saturate the output to full scale.

18. Inside a SAR ADC
This is a simplified diagram of what is inside a SAR ADC. The “DAC” and “Comparator” are not the same as those which can be controlled from user firmware. The IDAC and comparators on the F36x family are independent peripherals which can be used simultaneously with the ADC.
At the ADC’s front-end, a switch is used to charge the sampling cap to a voltage and then hold the voltage during the conversion. The point at which the switch changes from the input pin to the comparator is the sample time.

19. SAR ADC: Tracking and Conversion
Note here that during the tracking phase, the sampling cap is being charged, and the front-end of the ADC looks like an RC low-pass filter. Ideally, the switch will be in the tracking position long enough to charge the sampling cap to the same voltage at the source.

20. SAR ADC: Settling Time Common Problem: Inadequate Settling Time
The ADC connects the sampling cap to the input circuitry during the tracking phase of the conversion. Settling time for the input circuitry must be included during the tracking phase.
Inadequate settling time will lead to measurement errors, especially when multiplexing channels
Inadequate settling time can look like “crosstalk” between mux channels
The ideal time to switch a mux is during the conversion, when the ADC is not tracking the input. This allows the maximum settling time for the ADC input.
Settling time should be observed regardless of whether the conversions are all being taken on a single channel or muxed through multiple channels.
“Crosstalk” is actually any signal on a different mux channel which affects readings on the current channel. It would be the same regardless of whether the mux were switching channels.

21. SAR ADC: Settling Time
During tracking, the sampling circuit of the ADC looks like an RC low-pass filter. We can determine the settling time requirements using the step response equation for such a circuit, if we know how much error we can tolerate.
VIN could be any voltage in the ADC’s input range, so let’s express it as a percentage of the voltage we want VC to reach. As VIN is the ideal outcome, we set it to 100% = 1.0: VC(t) = 1.0 x (1-e(-t/RC))
The next few slides derive the settling time equation we use for our ADCs.

22. SAR ADC: Settling Time
The voltage we want VC to reach before the conversion happens is going to be determined by the LSB size of the ADC. We will use the variable SA (settling accuracy) here to represent a fraction of 1 LSB. Therefore, the error we can tolerate (VERR) becomes SA x (1/2N). A good rule of thumb is to set SA to ¼.
The voltage VC at the time of interest can now be specified:
VC(t) = SA x (1/2N).
Replacing VC(t) in the original equation gives us:
1.0 - SA x (1/2N) = 1.0 x (1-e(-t/RC))
We can simplify the equation to:
2N /SA = e(t/RC)

23. SAR ADC: Settling Time
We now need to solve for time. Taking the natural log of both sides gives us:
ln(2N /SA) = ln(e(t/RC))
ln(2N /SA) = t/RC
t = ln(2N /SA) x RC
“R” is the total series impedance: (RMUX + RSRC)
“C” is the sampling capacitor: CSAMPLE.
Therefore, the required settling time (in seconds) for a given level of accuracy is:
t = ln(2N / SA) x (RMUX + RSRC) x CSAMPLE
where:
N = ADC resolution in bits
SA = settling accuracy
For the purpose of this course module, you can put in a delay loop after starting the conversion, as shown below:
AD0BUSY = 1;
for (Delay = 0; Delay < 300; Delay++);
However, it is good programming practice to find out what the maximum settling time is and setting a delay based on that.

24. SAR ADC: Quantization of an Input Signal
The following slides lead us through a conversion on a 4-bit SAR. The examples use an input voltage of 1/3 VREF to illustrate the process.
The diagram above shows the binary decision tree for a 4-bit SAR ADC
The dark lines represent possible decision points for each bit
During the course of a 4-bit SAR conversion, the ADC will make four comparisons to determine the output word

25. SAR ADC: Quantization of an Input Signal
The first comparison is made at the MSB of the converter, which represents ½ VREF
An input signal of 1/3 VREF is less than the comparison voltage, so the result for the MSB will be 0

26. SAR ADC: Quantization of an Input Signal
The actual conversion is performed by the SAR DAC and the comparator
Each comparison takes one or more SAR clocks

27. SAR ADC: Quantization of an Input Signal
The second comparison is made on the next bit, which represents ¼ VREF
An input signal of 1/3 VREF is greater than the comparison voltage so the result for Bit 2 will be 1

28. SAR ADC: Quantization of an Input Signal
As the results are determined for each bit, they are loaded back into the SAR DAC

29. SAR ADC: Quantization of an Input Signal
The next comparison is at the level of 3/8 VREF. This is equivalent to ¼ VREF from Bit 2 plus 1/8 VREF.
An input signal of 1/3 VREF is less than the comparison voltage, so the result for Bit 1 will be 0.

30. SAR ADC: Quantization of an Input Signal
The final comparison for the LSB is at 5/16 VREF. This is equivalent to ¼ VREF from Bit 2 plus 1/16 VREF.
An input signal of 1/3 VREF is greater than the comparison voltage, so the result for the LSB is 1.

31. SAR ADC: Quantization of an Input Signal
The result is not perfect, but it is as close as the ADC can get with its limited resolution.
The final result (0101 binary, 5 decimal) is now determined
Our input voltage of 1/3 VREF ( VREF) has been quantized to 5/16 VREF ( VREF)

32. SAR ADC: Quantization of an Input Signal
When the final comparison is complete the result is written to the ADC’s output register

33. SAR ADC: Conversion Time
The conversion time required by the ADC is determined by the speed of the SAR clock
The SAR clock speed does not determine output word rate (this is determined by the start-of-conversion source)
Common Problem: SAR clock is too fast
Running a SAR with a clock that is too fast will lead to settling time problems with the internal SAR DAC
This will generally look like a linearity or missing code problem
The SAR Clock should be as close to the maximum specification as possible, but not faster—this minimizes conversion time and allows for maximum input tracking time

34. ADC Specifications

35. ADC: Specification Table

36. ADC: Basic Specifications
Number of bits or resolution
Equal to the number of bits in the output word
Digital specification – has little to do with analog performance
Output rate or throughput rate
Equal to the number of output samples produced per second
Defines the usable bandwidth of the ADC
Sampling rate
Equal to the frequency at which the input is sampled
Typically the same as output rate for a SAR converter, but much faster than the output rate for oversampling architectures like Delta-Sigma
It is very important to note that the “Resolution” of a converter is a digital specification. It says very little about the performance of an ADC, as it is simply the number of digital bits in the output word. An ADC can have a large number of bits in its output word, but not all of them may be usable. Yet this is one of the first things people look at when choosing a converter!

37. ADC: Offset Error
The Offset Error of an ADC is a constant error which causes a shift of the transfer function
Note that the slope of this transfer function is the same, it has simply been shifted up by a constant value.

38. ADC: Offset Error
The effect of offset error is identical to adding a fixed amount of voltage to the input

39. ADC: Offset Error
As an example, consider a 10-bit ADC using a 2.5 V reference
We will use the equation for calculating the ADC output code to show the effect of offset error:
Output = (VIN / VREF) x 2N; N = 10; VREF = 2.5 V
An offset error of 10 mV is like adding 10 mV to the input voltage
With the ADC input voltage at 0 V, it will look like +10 mV is at the input:
Ideal output : 0 V / 2.5 V x 1024 = Output code of 0
Output with offset : 10 mV / 2.5 V x 1024 = Output code of 4
4 – 0 = +4 codes of offset error
With the ADC input voltage at 1 V the same code error at the output will be seen:
Ideal output : 1 V / 2.5 V x 1024 = Output code of 410
Output with offset : 1.01 V / 2.5 V x 1024 = Output code of 414
414 – 410 = +4 codes of offset error
This example shows how the ADC transfer function is affected by the same amount at different points due to offset error.

40. ADC: Slope Error
The Slope Error of an ADC causes the slope of the ADC’s transfer function to change
Slope error causes the “angle” of the ADC transfer function to change. Note that this error gets worse towards the full scale of the transfer function.

41. ADC: Slope Error
The effect of slope error on an ADCs transfer function is identical to changing the value of the reference voltage used

42. ADC: Slope Error
As an example, consider a 10-bit ADC using a 2.5 V reference:
We will use the equation for calculating the ADC output code to show the effect of slope error:
Output = (VIN / VREF) x 2N; N = 10; VREF = 2.5 V + error
A 1% slope error is like adding 1% to the voltage reference
2.5 V x 101% = V
Changing the voltage reference changes the LSB size of the converter
For small input voltages, this error does not appear in the output word of the ADC:
Ideal output : 0.1 V / 2.5 V x 1024 = Output code of 41
Output with slope error : 0.1 V / V x 1024 = Output code of 41
41 – 41 = 0: No difference seen at output
As the input to the ADC rises, however, the error due to the 1% slope difference increases, and appears in the output word of the ADC:
Ideal output : 1 V / 2.5 V x 1024 = Output code of 410
Output with slope error : 1 V / V x 1024 = Output code of 406
406 – 410 = -4 code difference seen at output
This example shows how the ADC transfer function is affected by different amounts across the transfer function due to slope error.

43. ADC: Quantization & Differential Non-Linearity
A perfect ADC has code widths of exactly 1 LSB. This means that the DNL error is 0 LSB.

44. ADC: Quantization and DNL
Differential non-linearity (DNL) is a measure of the step width of the output codes from an ADC, or how much input voltage each discrete step represents
Ideally, each output code change of the ADC represents exactly 1 LSB of input voltage change
If DNL error is too severe, the result can be missing codes or a non-monotonic transfer function
Missing Code: A code which the converter never produces, regardless of input voltage
Non-monotonic: when a positive change in input voltage results in a negative change in output code (or vice-versa)

45. ADC: Missing Code

46. ADC: Non-Monotonic

47. ADC: Integral Nonlinearity
Integral nonlinearity (INL) of a converter is the worst-case deviation between the actual ADC transfer function and the ideal straight line
INL is caused by the accumulation (integral) of individual DNL errors along the transfer function of the ADC
INL is commonly specified using either the “end-point” method or the “best-fit straight line” method
End point method
End points of actual transfer function are determined, and the ideal straight-line reference is the line between them
Best-fit straight line method
The closest approximation to the actual transfer function is found and used as the straight-line reference
Although the two methods essentially provide the same information, it is important to know how INL is specified by a manufacturer.

48. ADC: INL End Point Method
The “bow” in the example here is not the only possible shape. The actual transfer function could be both above and below the straight line reference.

49. ADC: INL Best-Fit Straight Line Method
This is the same example, but using a best-fit curve.

50. ADC: Noise
The grey horizontal lines represent code boundaries. The bar graph on the right hand side shows each code in this visible range, and a count of how many times that code occurred during the sample set.
When the noise in a system is contained within 1 LSB of the ADC, the ADC will output a single code continually

51. ADC: Noise
Noise can come from the ADC or the input signal itself.
With slightly more noise in the system, the ADC output codes will vary, even for a constant input
Most of the conversions result in the same ADC code, but noise causes some conversions to produce adjacent codes

52. ADC: Noise
Note that with just the ADC samples here, there is not enough resolution to get any closer to the actual input. However, averaging samples together provides a means to get finer resolution.
If the input voltage with the same noise is shifted slightly up or down, more than one output code will “share” the bulk of the samples
The average value of the output in the above plot is in-between two adjacent ADC codes (i.e. a fractional value)

53. ADC: Noise
A Histogram can be a useful tool to visualize the effects of DC noise in a system.
The noise in this diagram is Gaussian (white noise). It follows a normal bell curve.
This is the same bar graph, turned on its side. A bar chart counting the occurrences of the outcome of different trials on a single event (i.e. samples of a DC signal) is called a histogram.

54. ADC: Noise
The Arithmetic Mean of the data is the average of all points in the data set
The larger the number of samples averaged together, the more precise the actual value can be determined.

55. ADC: Noise
The standard deviation (Sigma) is a statistical number that helps define the range of expected values
Approximately 68% of all values are within +/-1 Sigma of the mean
Sigma is calculated as the rms value of all deviations from the mean

56. ADC: Noise
Statistically, 99.9% of data points will be within +/-3.3 Sigma of the Mean value
This is often used to estimate the peak-to-peak noise of a system
Some manufacturers use +/-3 standard deviations to specify noise in their ADCs. This represents about 95%.

57. ADC: Common DC Noise Specifications
RMS Noise
Root-mean-square noise: equivalent to one standard deviation (Sigma) of a DC sample set
Peak-to-Peak Noise
Statistical number based on 99.9% confidence interval
Equivalent to +/- 3.3 Sigma
Both of the above can be measured by collecting a data set with a DC input
The above are DC specifications – how does the ADC respond with a constant input?
Note the last point, as it will partially be the focus of one of our lab measurements later.

58. ADC: How to get rid of Noise
If there is >1 LSB of noise in a system, averaging multiple samples together can yield a result with better noise resolution than the converter itself
One way to do this is to set up an ADC interrupt which averages a certain number of samples before giving an output
As mentioned earlier, just increasing the resolution of the ADC (number of bits) may not decrease the noise.

59. ADC0: Averaging Multiple Samples
Example Code for ADC interrupt for 4 samples:
// count = 0 initially
if (count < 4) {
Accumulator += ADC0;
count++; }
else {
Output = Accumulator / 4;
This code is part of the ADC0 interrupt. The variable Accumulator accumulates 4 inputs before they are averaged and sent to the variable Output.

60. ADC: Common Dynamic Specifications
SNR: Signal-to-Noise Ratio
Ratio of full-scale signal to noise components—excludes distortion
In audio applications (telephone, stereo), noise can be heard as a faint hiss
THD: Total Harmonic Distortion
Ratio of the fundamental signal to harmonically-related frequencies
In audio applications, harmonic distortion often sounds “tinny”
SINAD or S/(N+D): Signal-to-Noise Plus Distortion Ratio
Ratio of full-scale signal to all noise and distortion, except DC
SFDR: Spurious-Free Dynamic Range
Ratio of full-scale signal to highest non-harmonic noise component
These are DYNAMIC specifications – how does the ADC perform with a changing input?
If you have two of SNR, THD, or SINAD, you can calculate the third.
SFDR is important for the presence of other signals in the converter output.
SNR can be improved by amplifying the signal at the transmitter end, and de-amplifying at the receiver end.

61. ADC: Dynamic Performance Measurement

62. ADC: PSRR PSRR: Power Supply Rejection Ratio
50 and 60 Hz are mains frequencies that often bleed through into electronic equipment which uses mains power. An ideal ADCs output will be completely unaffected by changes in the supply voltage. PSRR is usually specified using a DC input and varying the supply. It is the ratio of change at the output to the change on the supply.
PSRR: Power Supply Rejection Ratio
Dependence of output signal on power supply fluctuations
Typically specified with DC and at 50/60 Hz

63. ADC: CMRR CMRR: Common Mode Rejection Ratio
An ideal ADCs output will be unchanged with changes in the common-mode voltage. CMRR is typically specified by tying the inputs together and moving the common-mode voltage. It is the ratio of the change at the output to the change in common-mode.
CMRR: Common Mode Rejection Ratio
Dependence of output signal on change in common-mode voltage
Important in differential measurements where the common-mode of the input signal is subject to change

64. IDAC Operation

65. What is a DAC? DAC is an acronym for digital-to-analog converter
DACs perform the opposite function of an ADC.
DAC is an acronym for digital-to-analog converter
A DAC takes a digital values as an input, and produces an analog signal (voltage or current) at its output

66. Output vs. Input
The output of a DAC is different from the input in two distinct ways
The input signal to the DAC is made up of discrete steps that are represented as digital codes (Discrete-time, quantized data), while the DAC output is a continuous voltage (Continuous-time signal)
The input signal is a series of discrete-time points, while the output is continuous in time

67. Different Types of DACs
There are a few different types of common DACs
Voltage DACs
Produce a voltage level proportional to the digital input
Use a voltage reference
Voltage is held steady at the output, current may vary
Current DACs
Produce a current proportional to the digital input
Use a current reference
Current is held steady at the output, voltage may vary
Two types: Current Sourcing and Current Sinking

68. Inside a Current Sourcing DAC
This is a simplified drawing of a current-sourcing DAC. More of the operational details are on the next slide.

69. IDAC Operation
A current reference is mirrored into a number of current sources of different values, equivalent to the “weight” of each bit in the converter.
Upon an output update request, the value written into the IDAC is used to open ‘0’ or close ‘1’ the switches corresponding to the weight of the data bits. The resulting current is combined to produce a current at the output.
The linearity of an IDAC is based on how well-matched these individual current sources are.

70. 4-bit IDAC
Shown below is a 4-bit Current-Sourcing DAC

71. 4-bit IDAC: Example
When the input is 15 all the switches are closed, resulting in an output of maximum current

72. IDAC Input/Output Range
The C8051F360 has a 10-bit IDAC. Therefore, it can receive 210 discrete inputs.
The maximum current output of the IDAC can be adjusted to three different settings; 0.5 mA, 1 mA, and 2 mA.
The IDAC has three different update modes, allowing the IDAC to update on a/an:
Write to IDA0H
Timer overflow
External pin edge

73. IDAC: Mode Details
In its default mode (IDA0CN.[6:4] = ‘111’), a write to IDA0H causes the IDAC to schedule an output update event. Note that a write to IDA0L will not cause the IDAC to update, hence, the write sequence should be IDA0L followed by IDA0H
In timer overflow mode, the IDAC output updates when the timer overflows. Writes to the IDA0H and IDA0L registers are held until the timer overflows
In external pin edge mode, writes to the IDAC data registers are held until and edge occurs on the CNVSTR input pin

74. IDAC: Setup
The following registers have to be modified when setting up the IDAC:
IDA0CN: IDA0 control
IDA0: IDA0 data word
Example setup:
IDA0CN = 0xF2; // Enable IDAC0 for 2.0 mA full-scale
// output; updated on writes to IDA0H
IDA0 = 0x8000; // IDA0 enabled

75. IDAC Performance Specifications

76. IDAC: Specifications
A DAC has many of the same specifications as an ADC, and most mean the same thing.

77. IDAC: Basic Specifications
Number of bits: Number of digital bits in the input word that can be represented at the output
One “LSB” of an IDAC is equivalent to:
Full-scale current output / 2N
For a 2 mA Full-scale 10-bit IDAC:
2 mA / 1024 = uA
Update rate/settling time: How often the output of the IDAC can be updated and settle to precision—analogous to ADC’s Output Word Rate
Output compliance
The voltage at the IDAC output pin requires headroom for the IDAC to operate within specification
Voltages outside the compliance range can result in linearity problems

78. IDAC: Data Word Mapping
The IDAC data registers (IDA0H and IDA0L) are left-justified, meaning that the eight MSBs of the IDAC output word are mapped to bits 7–0 of the IDA0H register, and the two LSBs of the IDAC output word are mapped to bits 7 and 6 of the IDA0L register.

79. IDAC: Additional Specifications
DNL: Differential Nonlinearity
INL: Integral Nonlinearity
PSRR: Power Supply Rejection Ratio
Much the same as the ADC specifications of the same names; refer to the ADC module for information on these topics

80. System-Level Error Compensation

81. System Error Sources
In any system there are a number of potential error sources
The goal is to minimize the effects of errors which are relevant to the system

82. Calibration of System Offset and Slope
Eliminating system-level offset and slope errors can be accomplished with digital calibration of the system at the output of the ADC
If there are no significant linearity issues, the transfer function of the entire system can be determined using two known points on a line

83. Single Point Calibration
If there is a specific point of interest in the system, a single-point calibration may be sufficient.
A single-point calibration eliminates error at one point on the system transfer function, and reduces overall error
Errors increase as the input moves away from that point

84. Two Point Calibration
Two-point calibration is particularly useful when the system is linear. If there is a nonlinear element in the system which can be described with an equation, two-point calibration can also be helpful.
A two-point calibration can eliminate offset and slope error across the entire system transfer function

85. Noise Reduction
Noise in a system can be reduced using analog or digital filtering techniques.
Simply averaging samples together will provide an efficient means of reducing the system noise. If the noise is white noise (Gaussian), averaging gives the most improvement.
If noise is correlated, it can still be reduced drastically using averaging or other filter techniques, but it is best to find and eliminate the noise source.
Digital coupling into analog circuitry
Switching regulators

86. Linearization
Some analog sensors require an amount of linearization, which can be performed in software using the appropriate calculations.
Thermocouples have a polynomial equation which describes their non-linear output
It is difficult to compensate for any nonlinearity inherent in an ADC or DAC, unless the nonlinearities can be easily described with an equation. Choose an ADC and DAC with good INL and DNL specifications for best results.