1. Rita De Masi IPHC-Strasbourg on behalf of the IPHC-IRFU collaboration
A fast, full-scale, CMOS pixel sensor with integrated zero-suppression and its evolution towards the ILD vertex detector
Rita De Masi
IPHC-Strasbourg
on behalf of the IPHC-IRFU collaboration
Motivations
Main features of MIMOSA-26
First applications and architecture extensions
Evolution towards the ILD-VTX
R&D
Summary and perspectives
SOCLE 2009

2. A vertex detector for the ILD
Physics goals + running conditions
single point resolution ~ 3m
material budget ~0.2% X0/layer
integration time 25 – 100 s
radiation tolerance > 300Rad, few 1011neq/cm2
P < 0.1 – 2 W/cm2
IP = a  b/psin3/2
a = 5m, b = 10m GeV
Radius: 16 – 60 mm for DL, mm for SL
SOCLE 2009

3. Features of CMOS sensors
Signal collection
Charges generated in epitaxial layer → ~1000 e- for MIP
Charge carriers propagate thermally
In-pixel charge to signal conversion
Advantages
High granularity
Thickness (~O(50mm))
Integrated signal processing
Issues
Undepleted volume limitations
radiation tolerance
intrinsic speed
Small signal O(100e-)/pixel
In-pixel m-circuits with NMOS
transistors only
SOCLE 2009

4. Basic performances
more than 30 different sensors designed, fabricated and tested (lab & beam)
extensive use of AMS 0.35mm OPTO process
room temperature operation
noise ~10-15e-
S/N ~ 15-30
detection efficiency ~100%
fake hit rate ~
Radiation tol. > 1MRad and 1013neq/cm2 with 10mm pitch (2x1012neq/cm2 with 20mm pitch)
spatial resolution 1-5 mm (pitch and charge-encoding dependent)
SOCLE 2009

5. Mimosa 26 column parallel architecture + integrated zero-suppression
(MIMOSA-22 for binary output + SUZE-01 for )
Fast full scale sensors: ~10kFrame/s
active area ~2 cm2
0.35 mm technology.
binary output
( m spatial resolution)
in-pixel CDS + preamp.
column level discrimination
power dissipated ~280 mW/cm2 (rolling shutter)
radiation tolerance (from M22): > 150kRad
Pixel array: 576 x 1152, pitch: 18.4 µm
Active area: ~10.6 x 21.2 mm2
13.7 mm
1152 column-level discriminators
Zero suppression logic
Memory IP blocks
21.5 mm
6 wafers x 77 sensors produced
27 (~700 m thick) + 6 (120 m thick) sensors tested: fabrication yield ~90%
SOCLE 2009

6. Laboratory tests Analogue response for 8 different sensors:
All pixels are alive.
Noise is uniform across the sensitive area (~2cm2).
Operated from 80 MHz (nominal) down to 20 MHz.
Noise and CCE (from 55Fe source) as expected (like MIMOSA-22).
Digital response for 21 different sensors:
All discriminators are operational at nominal speed.
Discriminator noise like MIMOSA-22.
Analogue + digital response:
Total noise 0.7 mV (~12-13 e- ENC) like MIMOSA-22.
Zero-suppression works as expected.
Full chain:
Fake hit rate 6N discri. threshold.
Performances unchanged for 20 < T < 40
Array of 660,000 pixels coupled to 1152 discriminators works ~ as expected
SOCLE 2009

7. EUDET beam telescope DUT Reference planes of EUDET Beam Telescope
Supported by EU FP6.
Infrastructure to support the ILC detector R&D.
Specifications:
- extrapolated resolution <2 mm
- sensor area ~2 cm2
- read-out speed ~ 10 kframe/s
- up to 106 hits/s/cm2 x z y
MIMOSA 26
CERN-SPS last Summer:
At first 3 MIMOSA-26 mounted in the BT demonstrator.
Residuals compatible with s ~3.5 – 4mm .
BT completely equipped with M26 (6 planes ~700 mm thick) last September.
SOCLE 2009

8. TAPI beam test TAPI = IPHC-Strasbourg BT for MIMOSA development.
Test in CERN-SPS.
120 GeV p- beam
6 MIMOSA-26 sensors (5 for telescope + 1 DUT) running simultaneously at nominal speed (80MHz).
3 x 106 triggers (~80% events reconstructed).
Detailed characterization ongoing.
SOCLE 2009

9. TAPI preliminary beam test results
Optimal discri. ~ 6 x noise
Efficiency > 99.5% with a fake hit rate ~ 10-4
s ~ 4.5 mm (under investigation)
Chip operational for the final EUDET BT
Architecture validated for its extension to other applications
SOCLE 2009

10. Mimosa 26 architecture: evolutions
RHIC Heavy Flavour Tracker
PHASE-1 (no )
640 x 640 pixels (30 mm pitch) → ~ 4cm2 active area
640 s integration time
Currently under test at LBNL
Final sensor (MIMOSA-26 like)
~1.1 million pixels (18.4mm pitch); ~200s integration time
Submission early 2010 → First data 2012/2013
Meeting with DoE this week for CD1
FAIR Micro Vertex Detector
Double sided readout
0.18 mm (40→20s integration time)
Improve radiation tolerance
Prototyping until 2012
SOCLE 2009

11. From MIMOSA-26 to the ILD-VTX
From 0.35 mm to (<)0.18 mm feature size
improved clock frequency, more metal layers, more compact peripheral circuitry, …
Extension for the outer VTX layers:
~100 ms integration time
~ 35 mm pitch and 4-5 bits ADC
(2 architectures developed at IPHC)
2x2 cm2
For the inner layers:
~ 15 mm pitch → binary readout.
Double-sided r.o. → i.t. ~ 50 ms.
Smaller feature size → 35 – 40 ms.
Exploit the DL design to reduce the i.t.:
elongated pixels on one side of the ladder
with depleted epitaxial layer ~10 ms time resolution may be possible.
SOCLE 2009

12. High resistivity sensitive volume
High resistivity epitaxial layer
Faster charge collection
Shorter path length (improved tolerance to non-ionising radiation)
Larger CCE (larger pitch possible without affecting the detection efficiency)
Exploratory sensor: MIMOSA 25 (0.6 mm technology)
e = 99.9% (99.5% after 3 x neq/cm2)
S/N ~60 (~30 after irradiation, ~25 for low res. epi-layer before irradiation)
0.35 mm technology run foreseen
Also: VDSM technology under study in coll. with CERN for sLHC (LePIX) (<< 1 ms)
Interest expressed also by the ALICE community
ZOOM
SOCLE 2009

13. Further developments: 3D
Benefits:
Increase integrated processing
100% sensitive area
Select best process per layer task
To be assessed:
Material budget?
Power dissipation?
Example
Tier1: charge collection
Tier2: analog signal processing
Tier3: digital signal processing
Tier4: data transfer
FNAL + IN2P3 + INFN + … consortium
First run (2 Tiers) submitted to Chartered-Tezzaron
 3 CAIRN prototypes submitted (low power, few ms r.o., delayed readout with timestamp).
 Heterogeneous chip (combining high resolution and small feature size).
SOCLE 2009

14. Summary and perspectives
First full scale sensor with high read-out speed
Architecture can be adapted to the different needs of inner and outer ILD-VTX layers
Inner: 2-sided r.o. + elongated pixels (high res. epi.) on DL design  ~10 ms.
Outer: increase pitch + ADC  ~100 s.
New perspectives: 3D integration technology
3 CAIRN prototypes submitted (low power, few ms r.o., delayed readout with timestamp).
Heterogeneous chip (combining high resolution and small feature size).
Particularly interesting for 1 TeV run.
More information on
SOCLE 2009