1. EE 501 Analog IC Design
Instructor Contact Information
Name: Degang Chen
Office: 2134 Coover Hall
Phone:
Office Hour: ??? Or any time convenient to you
Please include "EE501" in the subject line in all communications to avoid auto-deleting or junk-filtering

2. EE 501 Analog IC Design
TA Contact Information
TA: Mr. Xu Zhang
Voice phone: (515)
Office: Coover Hall
Office hour: TBA
Xu will help you with your Labs and your projects
Senior graduate students in 3102, 3108, 3011, 3201, and 2201 may also be able to help with your Cadence simulation.

3. EE 501 Analog IC Design Student Introduction
TA and me your contact information
For us to contact you
Brief intro
Name, and nick name if you have one
Advisor
Research Area
MS/PhD? Which year
IC design experience
Cadence experience
Study / lab / project partners

4. Class Webpage Please check the page for
Please check the page for
Announcements
Class notes
HW assignments
Reference reading materials
Project requirements
Class policy and other info

5. Student behavior expectations
Full attendance, except with prior-notified excuses
On-time arrival
Active participation
Ask questions
Answer questions from instructor or students
Help each other
Promptly report/share problems/issues, errors/typos in slides, misspoken words by instructor, …
cc TA and me, stating you are working on a lab, and describing the issue

6. Prohibited behaviors Any foul language or gesture
Comments to other students that are discriminatory in any form
Any harassments as defined by the university
Academic dishonesty
No alcohol, drugs, or any other illegal / improper substances

7. Accommodation/Assistance
Please let me know if you
Have any special needs
Have disability in any form
Have any medical/mental/emergency conditions
Have field trips / interviews
Have special requests
Want me to adjust lecture contents/pace
Can also consult me if you
Would like to seek advice on any professional or personal issues
Would like to have certain confidential discussions

8. Final Grade Weighting Laboratory: 15 points
Design projects: 15 points each
Homework: 15 points
Midterm Exam: 15 points
Final Exam: 25 points
Bonus:
Classroom participation: up to 5 points
Original creative work (publishable/patentable work): grade upgrade

9. Final Grade Scale A: 95+ A-: 90 – 95 B+: 85 – 90 B: 80 – 85
NR: <80 as default
If a grade is requested:
B-: 75-80
C+: 70-75
C: 65-70
F: <65

10. Laboratory Official required laboratories start in week 2
Optional lab 0 will be provided for this week
Each lab is for either 1 week or 2 weeks
A lab report is due at the beginning of the next lab
Lab report will be grade 1 week later
No lab in the project-due week, and possibly the week before or after

11. Optional Lab 0
Students with any of the following do not need to do lab 0
have taken ISU EE435
have IC design/layout experience from industry
have taken an IC design course using Cadence
have otherwise had >50 hours using Cadence tools for circuit design and simulation
assignment will be posted ASAP
TA will be available for help

12. Lab reports Lab report should be brief, and consists of the following:
Briefly state why you did the lab (purpose)
Briefly describe the main tasks and how you did them (what and how)
Briefly describe the results (with graphs, tables, explanatory captions)
Briefly state what you have learned
Additional comments, problems, doubts, …
For each day the report is late, 10% (1 or 2 points) will be deducted

13. Homework Assignments One assignment every 1 or 2 weeks
Each assignment will have 10 problems.
Each problem is worth 1 point, regardless of level of difficulty
Total number of assignments: 7~8
Due date: one week after it is posted unless otherwise specified
Late HW policy: 1 point penalty for each calendar day it is late.

14. Design Project Assignments
For each project, the preliminary project report due date will be posted.
After that, students will make presentations about their project.
After the presentation, you will be given time to make updates on your report and presentation.
The final due date for the presentation and report will be announced at the presentation time.
Penalty for late submission: 1 point per day for either the preliminary or final submission.

15. Exams One midterm exam in week 7 or week 8
Date to be determined by majority vote
Final exam time will be as specified by the university
Both exams will be closed-book, closed-notes, for individual work, with one sheet (US letter size, both sides) of formulae allowed

16. Course Description
Design techniques for analog and mixed-signal VLSI circuits.
Amplifiers: operational amplifiers, transconductance amplifiers, finite gain amplifiers and current amplifiers.
Linear building block: differential amplifiers, current mirrors, references, cascoding and buffering.
Performance characterization of linear integrated circuits: offset, noise, sensitivity and stability.
Layout considerations, simulation, yield and modeling for high-performance linear integrated circuits.
CAD tools: Cadence.

17. Course Objectives
Understand fundamental concepts related to sources of non-idealities, matching, noise, nonlinearities, and stability.
Design and analyze key building blocks.
Design and analyze multistage op amps for low voltage, low power, high gain, and high speed applications.
Experience floor planning, analog layout, corner simulation, yield assessment, design for test, and test planning.

18. Prerequisite by topics
Proficiency and fluency in using Cadence, Synopsis, and other IC design and simulation tools
Knowledge of basic amplifier structures, their large signal and small signal analysis, and computation of their gain, bandwidth, impedance and so on.
Knowledge of how transistors work, including various operation regions.
Knowledge of signals and systems, including poles, zeros, transfer functions, frequency response, transient response, stability, phase margins, and so on.
Knowledge of semiconductor fabrication and how transistors, resistors, capacitors, diodes, etc. are made.
Knowledge of probability, random variable, pdf’s, noise, signal to noise ratio, noise transfer, and so on.

19. Fabrication Privilege
Circuit fabrication is not required for the course
It is offered free as a privilege
Requirements for this privilege
Design review with detailed simulation results demonstrating that circuit is highly likely to work
Sufficient testing plan (what to measure and how)
Promise to test (availability and commitment of time)
Register in ee590H CD and submit a report to MOSIS
Benefits:
Valuable experience
Increased marketability
Get one or two credits for fabrication and testing
Limits: max two submissions per student

20. Text Book
Allen and Holberg, CMOS Analog Circuit Design, 3rd Edition, Oxford, 2011
Hastings, The Art of Analog Layout, Prentice Hall, 2nd ed
Available at Amazon
Significant discounts vs bookstore
International editions from Taiwan or Singapore

21. References
Gray, et al, Analysis and Design of Analog Integrated Circuits,  5th Ed., Wiley, 2009
William Liu, Mosfet Models for Spice Simulation, Including BSIM3v3 and BSIM4, Wiley-IEEE, 2001
Daniel P. Foty, MOSFET Modeling With SPICE: Principles and Practice, Prentice Hall, 1996
Yannis Tsividis, Operation and Modeling of the MOS Transistor, Oxford University Press; 2nd edition (May 1, 2003)
Laker and Sansen, Design of Analog Integrated Circuits, McGraw Hill, 1994
David Johns & Ken Martin , Analog Integrated Circuit Design, John Wiley & Sons, Inc. 1997
Behzad Razavi, Design of Analog CMOS Integrated, CircuitsMcGraw-Hill, 1999
Geiger, et al, VLSI Design Techniques for Analog and Digital Circuit, McGraw Hill, 1990
Baker, CMOS Circuit Design, Layout and Simulation, IEEE Press, 1997
Alan B. Grebene, Bipolar and MOS Analog Integrated Circuit Design (Wiley Classics Library), 2001

22. Collaboration and helping each other
For tasks intended for group work, you are expected to find a partner and share the tasks among the group members. In a group project, effective teamwork is critical to maximize the productivity of the whole group. In the submitted work, identify components and indicate percentage contribution by each member to each component.
For tasks not intended for group work, individual submission is required. In this case, you are encouraged to discuss among your friends on how to attack problems. However, you should write your own solution. Copying other people’s work is strictly prohibited.

23. Academic dishonesty
The class will follow Iowa State University’s policy on academic dishonesty. Anyone suspected of academic dishonesty will be reported to the Dean of Students Office.

24. Harassment and Discrimination
Iowa State University strives to maintain our campus as a place of work and study for faculty, staff, and students that is free of all forms of prohibited discrimination and harassment based upon race, ethnicity, sex (including sexual assault), pregnancy, color, religion, national origin, physical or mental disability, age, marital status, sexual orientation, gender identity, genetic information, or status as a U.S. veteran.
Any student who has concerns about such behavior should contact his/her instructor, Student Assistance at or or the Office of Equal Opportunity and Compliance at

25. Disability accommodation
Iowa State University complies with the Americans with Disabilities Act and Sect 504 of the Rehabilitation Act.
If you have a disability and anticipate needing accommodations in this course, please contact (instructor name) to set up a meeting within the first two weeks of the semester or as soon as you become aware of your need.
Before meeting with (instructor name), you will need to obtain a SAAR form with recommendations for accommodations from the Disability Resources Office, located in Room 1076 on the main floor of the Student Services Building.
Their telephone number is or . Retroactive requests for accommodations will not be honored.

26. Religion based conflict
If an academic or work requirement conflicts with your religious practices and/or observances, you may request reasonable accommodations. Your request must be in writing, and your instructor or supervisor will review the request. You or your instructor may also seek assistance from the Dean of Students Office or the Office of Equal Opportunity and Compliance.