EMC for integrated circuits

EMC for integrated circuits
Mesure CEM Seminar at University of Missouri at Rolla Monday 10th, 2004 EMC for integrated circuits Etienne SICARD Professor at INSA Toulouse, FRANCE 2018/9/16 E. Sicard - EMC for ICs

Toulouse: we are Airbus
2018/9/16 E. Sicard - EMC for ICs

Toulouse: where I come from
Paris 400 miles Bordeaux Grenoble Toulouse Tarbes Aix 2018/9/16 E. Sicard - EMC for ICs

Contents The EMC research group EMC Issues IC emission
Measurement of emission IC susceptibility Measurement of susceptibility Green chips EMC models Future & conclusion 2018/9/16 E. Sicard - EMC for ICs

1. The EMC research group www.ic-emc.org 2018/9/16
E. Sicard - EMC for ICs

Research group EMC for ICs
1. The EMC research group Research group EMC for ICs European Projects MESDIE, EmcPack French Std Committee UTE Standardization groups IEC, IBIS L. Courau (B. Vrignon) A. Soubeyran (E. Lamoureux, E. Vialardi) C. Huet IUT Tarbes France J.M Dienot S. Baffreau INSA Toulouse France E. Sicard S. Bendhia ENSA Agadir, Morroco L. Bouhouch, M. Mediouni C. Lochot (C. Labussiere) PhD thesis (name) Research Contracts Alsthom-Pearl (G. Lourdel) Status in May 2004 2018/9/16 E. Sicard - EMC for ICs

2. EMC issues 2018/9/16 E. Sicard - EMC for ICs

2. EMC issues Emission Susceptibility
Mesure CEM 2. EMC issues Mobile phone Personal entrainments Safety systems Emission Component Equipments Boards Susceptibility Susceptibility to radio frequency interference is illustrate in the case of a very high radar wave illuminating an airplane. This situation is very common at the proximity of airports. A Giga-watt pulse is received by the the plane, which captures some energy which may flow to the equipment, the board and finally to the component. On the other hand, the parasitic emission due to the integrated circuit inside a car may jeopardize the correct behavior of personal devices such as mobile phones, and RF links. In some case, the parasitic energy may be high enough to parasite the safety systems of the car. Main demand: automotive and aerospace industry 2018/9/16 E. Sicard - EMC for ICs

2. Emc Issues Between Ics in a board RF MCU Memory Bus control DSP ADC
1000 Between Ics in a board RF MCU Memory Bus control DSP ADC DAC Test Inside the IC System in package Susceptibility level (dBmA) -40 -30 -20 -10 10 20 30 40 50 1 100 f (MHz) Sum of perturbations Susceptibility level High risk of interference Safe interference margin Unsafe margin 2018/9/16 E. Sicard - EMC for ICs

3. IC Emission 2018/9/16 E. Sicard - EMC for ICs
Mesure CEM 3. IC Emission This presentation deals with the integrated circuit floorplan. 2018/9/16 E. Sicard - EMC for ICs

Probably EMC compliant
Mesure CEM 3. IC emission Low parasitic emission is a commercial argument dBµV 20 40 60 80 100 10 1000 FM GSM RF Probably EMC compliant Not EMC compliant Supplier A B Frequency(MHz) Less decoupling components Lower board quality Less troubles Lower equipment cost New: IC suppliers earn money thanks to EM compliance Low parasitic emission is a key commercial argument. The characterization of the electromagnetic emission is usually presented in frequency domain, log/log, with the frequency in X axis, and the emission level in dBµV in Y axis. 0dBµV is 1µV, 40dBµV is 100µV, 80dBµV is equal to 10mV. For automotive applications, three frequency bands are worth of interest: the FM band near 100MHz, the short distance radio links near 400MHz and the mobile phone 900,1800 and 1900MHz. The IC in red (Supplier A) exhibits a very high level of harmonics in the three “sensitive” bands. Electronic systems using this component could not comply EMC regulations. The same IC from an other supplier B, pin-to-pin compatible, features a significantly lower level of emission, which will probably be compliant with the customer’s specifications. 2018/9/16 E. Sicard - EMC for ICs

Basic mechanism for emission: gate current through package inductor
Mesure CEM 3. IC emission Basic mechanism for emission: gate current through package inductor VDD VDD Pull Up IDD (0.5mA) Pull Up 1 1 Vin ISS (0.5mA) Output capa Output capa One of the major source of perturbation is the current flowing inside each elementary gate of the integrated circuit. Let us consider the CMOS inverter, supplied by a high voltage VDD (2V in 0.18µm) and ground VSS (0V). When the input falls to 0 (i.e logic level “0”), a current (around 0.5mA) charges the capacitance through the pull up device. When the input rises to 2V, that is a logic level “1”, a similar current flows through the pull down device and discharges the capacitance. Pull Down Pull Down VSS VSS Microwind 2018/9/16 E. Sicard - EMC for ICs

3. IC emission Noise linked to package VDD=2.5V Lead = 10mm
Mesure CEM 3. IC emission Noise linked to package VDD=2.5V Lead = 10mm 100mA in 1ns CHIP We illustrate here the common mechanism that transforms the internal current switching into a parasitic emission. Let us consider a quad-flat-packaging (QFP) with 44 pins, with a chip placed in the center of the package. The die occupies only a reduced surface of the package. The die is connected to the package using bonding wires. The supply wire length from the die to the external printed circuit board is approximately 10 mm. The usual rule of thumb considers 1nH/mm. What is the consequence of a 100mA peak with a rise/fall time of 1ns? The answer may be found using the approximation of the voltage drop in each inductance (Ldi/dt). We find around 1V, that is confirmed by measurement. Lead = 10mm VSS=0.0 Noise > 1V 2018/9/16 E. Sicard - EMC for ICs

Increased Emission problems
Mesure CEM 3. IC emission Effect of scale down Current amplitude keeps constant Faster switching Volt Old process Stronger di/dt New process Time Current Old process With the technology scale down, the supply voltage is reduced and the signals switch faster within interconnects (From voltage to scaled voltage). In 0.18µm technology, the switching is about 100ps (Pico-second or second), with a 2V swing. Concerning currents, the amplitude of elementary peaks appearing on supply lines of each elementary gates are sharper, but their amplitude remains constant (0.5mA in 100ps, per gate). Consequently, stronger di/dt are observed, leading to increased emission problems. Increased Emission problems di/dt New process Time 2018/9/16 E. Sicard - EMC for ICs

3. IC emission Trend: higher noise, wider spectrum
Important frequency bands 2005 2010 100 (dBµV) 80 60 64 bit? 32 bit 40 16 bit 20 F(MHz) 10MHz 100MHz 1GHz 10GHz Limit 1999 2003 2018/9/16 E. Sicard - EMC for ICs

4. Measurement of Emission
Mesure CEM 4. Measurement of Emission This presentation deals with the integrated circuit floorplan. 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 4. Measurement of Emission TEM method, issued for USA SAE J1752/3 Specific board 50cm 10x10cm Measure For the measurement of parasitic emission radiated by the integrated circuit, the most popular method is based on a TEM cell (i.e Transverse Electromagnetic assumption), consisting of a shield box and a window for inserting the board 10x10cm. The chip under test is fixed in the inner side of the board, and radiates inside the chamber, not outside. A metal plate, inside the box, captures the chip emission, which is converted and plotted in the frequency domain by the spectrum analyzer. The frequency limit of this method is around 1GHz, due to the physical dimensions of the chamber. Shielded box To spectrum analyzer The best radiated mode method (IEC ) 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 4. Measurement of Emission GTEM cell : up to 18 GHz Shielding Absorbant Schaffner 250 « Sae » DUT Septum One very important measurement method for parasitic emission above 1 GHz in the GTEM cell (Giga Hertz TEM). Several sizes of GTEM cells are proposed, from IC size (10 x 10 cm aperture) up to complete system characterization. The GTEM cell enables measurements up to 18 GHz. Again the physical dimension of the shielding and the inner septum are 50 ohm adapted. The best candidate for radiated emission 1-10GHz 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 4. Measurement of Emission German Std VDE UK → IEC International Standard Spectrum Analyser IC Concerning conducted mode emission, the most common method is based on a 1 ohm resistance added in serial to the ground supply. The voltage sent to the spectrum analyzer is the image of the current flowing on the ground pins of the integrated circuit. The method is issued from the German standardization group VDE. The method is limited to 1GHz, although measurements may be performed at higher frequencies. The problem is the inductance behavior of the 1 ohm resistance above 1GHz. 1ohm 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 4. Measurement of Emission Magnetic Probe SAE J1752/2(Japan) → IEC International standard Receiver Probe DUT An other method radically different from the 1ohm conducted probe is the magnetic loop. This loop is connected directly to the spectrum analyzer. It enables rapid investigations of high peaks of radiated emission over the device under test. Other components Can locate high levels of emission, but depends on orientation 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 4. Measurement of Emission Magnetic Probe (IEC ) Y axis Amax plot Y axis IC location dBµV An exploitation example of peak emission is given in this slide. We define Amax as the maximum peak appearing in the instant spectrum. At each X, Y location, the Amax [X, Y] is extracted, and plotted according to a palette of colors. This method give valuable information about the location of high magnetic fields, specifically over the IC die area and the package leads. Some scanning systems have spatial resolution as small as 1µm. X axis Amax Near field scanning helps to improve IC design Near field is a key method for System-in-Package EMC freq X axis 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 4. Measurement of Emission Summary Radiated DC-1GHz SAE J1752/3 IEC TEM Cell Radiated DC-18GHz GTEM Cell Conducted DC-1GHz This slide summarizes the most common emission measurement methods. The internal standardization has been completed in 2001 for TEM, 1ohm. The process for standardization is undergoing for the GTEM cell. UK IEC VDE 1 1997 1999 2001 2003 2005 2018/9/16 E. Sicard - EMC for ICs

5. IC Susceptibility 2018/9/16 E. Sicard - EMC for ICs
Mesure CEM 5. IC Susceptibility This presentation deals with the integrated circuit floorplan. 2018/9/16 E. Sicard - EMC for ICs

5. IC Susceptibility Multiple electromagnetic noise sources 1W
Mesure CEM 5. IC Susceptibility Multiple electromagnetic noise sources TV VHF Hobby GSM TV UHF Radars Satellites MWave Badge DECT BaseStat 1W Frequency 1MW 1KW 1GW Weather radar 3 MHz 30 MHz 300 MHz 3 GHz 30 GHz 300 GHz Power 1mW HF VHF UHF SHF xHF THF This slide illustrate the emission power of several electronic devices. Several device exist in the range 1-5 GHz such as DECT digital phones (10mW power), mobile phones (1W), GSM base stations (100W), microwave (1KW), TV emits (10KW). Sources over 1MW are antennas for satellite link, military and weather radar. The frequency band 3-30MHz is called High frequency, MHz Very High Frequency, 300MHz-3GHz Ultra-High Frequency, 3GHz-30GHz Super High Frequency, GHz extremely High Frequency, and 300GHz-3THz (Tera-Hertz) Tremendously High Frequency. 2018/9/16 E. Sicard - EMC for ICs

5. IC Susceptibility More I/Os, less noise margin Supply (V) 5.0
Mesure CEM 5. IC Susceptibility More I/Os, less noise margin Supply (V) 5.0 I/O supply 3.3 2.5 Core supply Susceptibility of integrated circuits to external perturbations is a key problem. The technology scale down offers the design of more complex integrated circuits, with more input/outputs. This means that the external interfacing is increased, leading to more possibilities for external signals to interfere with the circuit. Moreover, the supply voltage is continuously increased, for reliability and low power requirements, which tends to reduce the noise margin of the IC and increase its susceptibility to external electromagnetic waves. 1.5 0.7 Technology(m) 0.5µ 0.35µ 0.18µ 90nm 70nm 2018/9/16 E. Sicard - EMC for ICs

6. Measurement of Susceptibility
Mesure CEM 6. Measurement of Susceptibility This presentation deals with the integrated circuit floorplan. 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 6. Measurement of Susceptibility BCI in CAN Bus (IEC ) Parasitic current Fault CAN Bus DUT Normal current Microcontroler Coil An example of BCI set up in the case of a CAN (Control Area Network) bus, widely used in automotive applications, is described in this slide. The parasitic current is injected by a coil which may alter the CAN driver information, and induce a fault inside the micro-controller. This method is limited to 400 MHz, due to the cut-off frequency of the injection coil. Inductive coupling to the network Parasitic current injected on the chip Limited to 1GHz 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 6. Measurement of Susceptibility BCI measurement example Current limit I(dBµA) Config 2 10 20 30 40 50 60 70 200 400 600 800 1000 1200 1400 1600 Current provoking failure Less sensitive More sensitive Config 1 Frequency limit An example of BCI measurement is presented in this slide, with 2 configuration set ups. One includes a typical circuit (lower curve) which exhibits a susceptibility weakness from 200 to 800 MHz. The second one (upper curve) shows an improved behavior, meaning a lower sensitivity to injected parasitic sinusoidal wave. For example, a 20dBµA RF current is sufficient to induces a failure for configuration 1 at 350MHz. In configuration 2, the required amplitude to induce failure is close to the maximum current (55dB). This spectacular improvement is done by appropriate filtering, protection, careful PC, package and IC floorplan routing. Frequency (MHz) 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 6. Measurement of Susceptibility Direct Power Injection « DPI » (IEC ) DUT High power wave Injection An important method to measure susceptibility of integrated circuits is the direct power injection, based on capacitor coupling. The interference wave form, such as burst or continuous sinus wave, is created using the signal generator. This RFI wave is amplified and superimposed on functional signals, via a coupling capacitance. Quite simple to use Very simple to modelize at low frequency Several set-up problems Limited 1 GHz 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 6. Measurement of Susceptibility DPI setup at INSA Signal generator Oscilloscope Device under test IEEE Bus Coupling Capacitance DUT 10W Amplifier Dout or Good signal Failure signal Printed Circuit Board PC Monitoring This slides illustrates the setup of the direct power injection method involving a software control of the injected power, a feedback through the oscilloscope which features envelope detection. The signal generator creates a sinusoidal wave with programmable amplitude and frequency. A small amplitude is generated first. While the signal is kept within a predefined envelope, the chip is considered as safe, and the amplitude is increased. When the signal goes out the envelope, an error message is sent to the control software, which stops the incremental power injection. A new frequency can be investigated, until the whole frequency range is analyzed. 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 6. Measurement of Susceptibility Workbench Faraday Cage from Philips (WBFC) IEC A method called Workbench Faraday Cage has been proposed by Philips and standardized under reference IEC This method is also used in emission measurements. It consists of placing the whole test board in the chamber and injecting the RF signal through the shielded box to the DUT. This limit is limited to 1GHz. Common mode methodology Frequency range 150kHz - 1 GHz. Emulates real case equipment. 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 6. Measurement of Susceptibility What is available above 1GHz? Power Amplifier Most methods limited to 1GHz The GTEM cell could be used as a RF source Its frequency limit is 18GHz (24GHz chamber now exist) Challenger: Reverberating Chamber Not standard available yet fixed The GTEM cell is a vary promising candidate for susceptibility analysis above 1GHz. Already in use for emission measurements, the GTEM cell is currently being proposed as an international standard for susceptibility too. Power around Watts should be injected leading to very strong electromagnetic fields inside the chamber (1000V/m) at the test location. 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 6. Measurement of Susceptibility Summary Conducted DC-400MHz Bulk Current injection IEC Conducted DC-1GHz IEC Direct power injection This slide summarizes the measurement methods used for susceptibility. Conducted DC-1GHz IEC Workbench Faraday Cage 1997 1999 2001 2003 2005 2018/9/16 E. Sicard - EMC for ICs

7. Green Chips 2018/9/16 E. Sicard - EMC for ICs
Mesure CEM 7. Green Chips This presentation deals with the integrated circuit floorplan. 2018/9/16 E. Sicard - EMC for ICs

7. Green Chips Rule 1: Reduce the serial inductance
Mesure CEM 7. Green Chips Rule 1: Reduce the serial inductance Why: because inductance is a major source of resonance 3.3V Exercise2: On-chip 8 bit ADC CHIP 2.5V 100mA in 1ns Q2: how many supply pins should be used? Adc Bga Viewer Exercise 1: target 150mV noise 50mA in 1ns CHIP We detail four rules to reduce parasitic emission. The first one consists in decreasing the serial inductance. Inductance is a major component that creates resonance, and resonance is the source of conducted and radiated emission. The inductance is an intrinsic component of each conductor. When the conductor is far from ground, the inductance is increased. A bonding wire has approximately a 1nH/mm inductance. A supply line within the chip has a 0.2nH/mm inductance. 0V Q1: how many supply pins should be used? 2018/9/16 E. Sicard - EMC for ICs

Canceled contributions
Mesure CEM 7. Green Chips Rule 2: Place VDD and VSS supply as close as possible Why: to reduce current loops that provoke magnetic field to increase decoupling capacitance that reduces fluctuations Added contributions Canceled contributions EM wave The second important rule consists is placing VDD and VSS supply as close as possible from each others. This reduces the surface of the current loop which provokes immediate parasitic emission, in radiated mode. A very bad pin assignment consists in one VDD supply on one side, one VSS supply on the other side. This lead to a maximum emitted parasitic energy. Consequently, the current wires placed together almost cancel the magnetic field and significantly reduce the radiated signature of the IC. Gains higher than 20dB have been observed in TEM cell measurements. current Lead Lead 2018/9/16 Die E. Sicard - EMC for ICs

7. Green Chips Rule 2: Place VDD and VSS supply as close as possible
Mesure CEM 7. Green Chips Rule 2: Place VDD and VSS supply as close as possible VSS VDD µm Supply grid starting 0.35µm Reduction of parasitic emission Strong current The best solution is to use a grid of supply network, for both VDD and VSS. This technique is widely used for CMOS technologies starting 0.35µm, where 5 metal layers or more are available. The distribution of current is rarely homogenous in all locations of the internal grid. Some parts handle small current density while other parts suffer strong current flows. Reduced current Simulation of current flow on a grid 2018/9/16 E. Sicard - EMC for ICs

7. Green Chips Rule 3: Add decoupling capacitance Why:
Mesure CEM 7. Green Chips Rule 3: Add decoupling capacitance Why: to keep the current flow internal to reduce the supply voltage swing Customer’s specification Parasitic emission (dBµV) 80 70 Volt 60 No decoupling 50 40 30 An on-chip capacitance between VDD and VSS acts as a current generator that supplies the chip and thus reduces the amount of current flowing through the leads. An efficient technique to implement on-chip capacitance consists in routing VDD and VSS power rails large, on the top of each other, with multiple junction capacitance whenever possible. The free area underneath the routing channel can be used to implement extra capacitance. The thin oxide gate capacitance may be used to generate high value capacitance (several nF), with yield limits when implementing very large gate areas. 1nF decoupling 20 10 time -10 1 10 f (MHz) 100 1000 2018/9/16 E. Sicard - EMC for ICs

7. Green Chips Rule 4: Identify & isolate Noisy blocks Why:
Mesure CEM 7. Green Chips Rule 4: Identify & isolate Noisy blocks Why: to reduce the injected noise How by locating fast signals with strong currents by separate voltage supply by substrate isolation By shunt resistance On-chip capa Shunt resistance Memory array Standard cells The 4th important rule consists in trying to identify the noisy blocks, and try our best to isolate them. In terms of EMC, we concentrate on fast signals which switch high power. We try to supply these circuits by separate supplies, and if possible, isolate substrate noise conduction by a bulk isolation, a feature available starting 0.18µm. Bulk isolation Analog Far from noisy blocks Separate supply 2018/9/16 E. Sicard - EMC for ICs

7. Green Chips New pin assignment Slight on-chip redesign
Mesure CEM 7. Green Chips (Almost a real story) Warning: Over current on pin 23 Ground bounce: voltage drop around 500mV (spec: 50mV) ADC measured resolution: 6 bits (required 10 bits) CAN bus erratic problems Emission 20dB over spec at 100MHz Send an expert and solve the problems NOW, otherwise we cancel the 10M$ contract Several tests were conducted by the customer and a huge list of problems appeared. Now that you learnt some rules about low emission floor-planning, you are probably able to understand the origin of the listed problems. In this case study, you act as an EMC engineer which is called urgently to improve the floor-planning of the chip (without changing the chip layout which would cost too much), in order to save the contract. New pin assignment Slight on-chip redesign 2018/9/16 E. Sicard - EMC for ICs

7. Green Chips CESAME test chip with ST-Microelectronics (CMOS 0.18µm)
6 identical core with various low emission strategies 2018/9/16 E. Sicard - EMC for ICs

7. Green Chips CESAME test chip measurements Normal core
Confirms the efficiency of low emission design techniques On-chip decap, shunt 2018/9/16 E. Sicard - EMC for ICs

8. Models for EMC simulation
Mesure CEM 8. Models for EMC simulation This presentation deals with models for electromagnetic compatibility simulation. 2018/9/16 E. Sicard - EMC for ICs

8. Models for EMC Simulation
Mesure CEM 8. Models for EMC Simulation EMC problems handled at the end of design cycle Version n° DESIGN FABRICATION Architectural Design Design Entry Design Architect Version n° EMC Measurements Conventional IC design methodologies consider the evaluation of parasitic emission level and susceptibility once the integrated circuit has been fabricated. Such methods often require a redesign with the help of EMC experts, which has a very import impact on the overall cost and time to market. Compliance ? NO GO GO + 6 months + $$$$$$$$ 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 8. Models for EMC Simulation Dream: find EMC problems before fabrication Design Guidelines Tools Traning DESIGN Architectural Design Design Entry Design Architect EMC Simulations Compliance ? The target methodology consists in adding specific tools, design guidelines and appropriate training in order to iterate in the design phases and to ensure the EMC compliance prior to fabrication. If the simulation flow is validated the IC once fabricated will comply to electromagnetic compatibility regulations. This flow should soon become reality as major IC manufacturer conduct research and development in this area, and start getting good results. However, tools are not mature, the design guidelines are somehow an expert-level knowledge, and the training is hard to setup due to the very wide aspects treated by EMC for ICs. Models FABRICATION NO GO EMC compliant GO 2018/9/16 E. Sicard - EMC for ICs

The EMC model must include the core and package model
Mesure CEM 8. Models for EMC Simulation The EMC model must include the core and package model Modelize the core the internal activity the supply network the I/O structure Core Core IC Modelize the Package using R,L,C The macro-model of an IC consists of two main parts: one related to the core of the integrated circuit, the other one related to the package. Concerning the core, the internal switching activity is the main concern. The supply network also needs a careful analysis, as well as the active inputs and outputs. Concerning the package, an R,L,C matrix representing the interconnect array is required. Package 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 8. Models for EMC Simulation A standard model for emission: ICEM VDD Rvdd Lvdd Limit of the die Cd Cb Ib VSS Rvss Lvss Here is the basic structure of the EMC model, as described in the international standard « ICEM », promoted by the French standardization group UTE. The die is modeled by a capacitor Cd (Decoupling VDD/Vss), a serial access resistor Rvdd, Rvss, a serial inductor Lvdd, Lvss, a block decoupling Cd and a current generator Ib. This simple structure is able to predict quite accurately the consequences of the current flow in terms of supply noise and emitted energy in a TEM cell chamber. ICEM model promoted by UTE (IEC ) Used by IC supplier/customer on a non-confidential basis Available in IBIS website or 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 8. Models for EMC Simulation Modelize the core Physical Transistor level (Spice) Interpolated Transistor level (Powermill) Difficult adaptation to usual tools Limited to 1 M devices Gate level Activity (Verilog) Simple, not limited Fast & accurate Huge simulation Limited to analog blocks The modeling of the core can be performed at various levels. We illustrate here three approaches. The first one, acting at physical level, consists in the analog simulation of the core. This approach is limited to small blocks, typically 100 to 1000 transistors. The current consumed on the VDD and VSS supply lines are accurately predicted. For large blocks, a working approach consists in the use of pseudo analog simulation, where the physical set of equations is replaced by an approximated tabulated array of data. This approach speeds up considerably the simulation, which remains at analog level, and gives the current flow on VDD and VSS almost as accurately as for the pure analog simulation. However, the supply voltages are considered perfect. For several millions of devices, the only remaining approach is based on the gate current approximation, using a statistical approach for elementary gate current. The total current is the sum of elementary currents, each one being characterized individually under typical loading and switching conditions. 1200 I(mA) Equivalent Current generator 1000 800 600 400 2018/9/16 200 E. Sicard - EMC for ICs time (ns) 20 40 60 80 100 120 140

Mesure CEM 8. Models for EMC Simulation Rely on Input Buffer I/O specification (IBIS) for R,L,C and buffer models [Component] ST74FCT16244 [Manufacturer] ST [Package] | variable typ min max | R_pkg m m L_pkg nH nH C_pkg pF 4pF [Pin] signal model R_pin L_pin C_pin 1 /1OE in1 2 1Y1 out1 3 1Y2 out1 4 GND GND 5 1Y3 out1 6 1Y4 out1 Here is an example of IBIS description file, for a quad flat pack packaging and a 16 bit buffer. We see a list of keywords, followed by the description of each pin of the IC, with some electrical parameters such as serial inductor L_pkg, serial resistor C_Pkg and lead-to-ground capacitor C_pkg. 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 8. Models for EMC Simulation Typical flow to compare IC emission simulations with measurements Measurements Simulations The complete flow for comparing measurements to simulations is given in this figure. Concerning simulation, our task is to define a model of the board including the IC, the package, the measurement probe and the test board. Each part requires some specific model. The measurement is done using a frequency analyzer of a high bandwidth oscilloscope. The fast Fourier transform and the appropriate post-processing transforms the measurement data into a plot of the dBµV versus frequency. 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 8. Models for EMC Simulation Conducted Mode 16-bit microcontroller -10 10 20 30 40 50 60 70 80 1 100 1000 f (MHz) dBµV EMC model Measurements DUT 1 To receiver Here is a concrete example of simulation compared with measurements, using the conducted 1ohm probe. The measurement is provided by a high quality frequency analyzer, and the model is given by a SPICE analog simulation in time domain, converted in the appropriate units (dBµV vs frequency) by fast Fourier transform. 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 8. Models for EMC Simulation Radiated Mode TEM cell To receiver 50  Cdie_septum Inductor coupling Lpack_vdd Rvdd Lvdd Cd Cb Ib Lio Lpack_vss Cio The same model applies well in the prediction of the spectrum emitted in the TEM cell by integrated circuits. The core model is then connected to the TEM cell using two elements: a capacitor Cdie_septum and a coupling between inductors. VSS Rvss Lvss Rsub Limit of the package Limit of the die 2018/9/16 E. Sicard - EMC for ICs

Radiated Mode 2018/9/16 E. Sicard - EMC for ICs

9. Future & Conclusion Extend emission models, measurements to 18GHz
Mesure CEM 9. Future & Conclusion Extend emission models, measurements to 18GHz Predict susceptibility Perturbation model IC model Time V ICEM core model? Supply disturbance model I/O disturbance model Improve system-on-chip compliance Study system-in-package EMC Finally, could the ICEM model be used in susceptibility? This is still an opened question but the UTE task force in France has started a debate and technical research on this topic. The goal is to propose some enhancements in the structural description of IC models in order to predict the first order response of the IC to external electromagnetic wave. Input pad model 2018/9/16 E. Sicard - EMC for ICs

Mesure CEM 9. Future & Conclusion The global context of EMC of ICs has been described IC Emission tends to increase with scale down Low emission design techniques exist at IC level EMC models can help predict emission Good correlation has been achieved up to 1GHz Soon, requirements up to 3-10GHz Some domains not well covered: susceptibility modeling, system-in-package EMC This presentation is now completed. We detailed how an IC design methodology including EMC modeling and prediction may help saving money. We described the structure of the IC macro-model that enabled and accurate prediction of conducted/radiated emission, through a reduced set of simple elements. Then, we explained how the model can be feed with physical data at printed circuit, package, I/O and core level. We showed interesting correlation between measurements and simulation for a conducted 1ohm and TEM cell approaches, up to 1GHz. The future of EMC models, for bandwidth up to 18GHz and susceptibility have also briefly been discussed. 2018/9/16 E. Sicard - EMC for ICs

Highlights Built and sponsored an international workshop on EMC of Ics
EMC Compo 02, EMC Compo 04 Developped on-chip noise sampling approach and test chips IEEE proceedings, IEEE trans Vlsi, IEEE trans Emc Edited a special issue on EMC of Ics, REE June 02, Microelectronics Journal June 04 Write book chapters on EMC of Ics IEEE Review of radio Sciences 2002, dedicated book in Kluwer 2005 Participate to major EMC conferences IEEE St Clara 04, EMC Europe 04, Date 04, EMC Zurich 05, etc.. Propose standards for EMC modeling of ICs ICEM, ICIM, Ibis improvments 2018/9/16 E. Sicard - EMC for ICs

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