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DAC architectures.

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Presentation on theme: "DAC architectures."— Presentation transcript:

1 DAC architectures

2 Tao Chen Office: Coover 3108

3 Last week: Unbuffered String DACs

4 You can also choose to make the fine segment using a ladder structure.
For the 3+3 bit structure, what resistance values should be used?

5 Current-Mode R-2R Ladder
RF IOut VOut Vout=RF*Iout

6 Current-Mode R-2R Ladder
RF IOut VOut

7 Current-Mode R-2R Ladder
Vref Vref/2 Total current: Vref/R I1 I2 RF IOut Ron VOut Series R can be used to adjust gain of DAC R_out is code dependent, leading to DAC nonlinearity if un-buffered But can use all NMOS switch, -tive gain buffer

8 Thermometer current DACs
Output node at virtual ground Each resistor contributes either 0 or Vref/R If input digital code = k, k of the 2N – 1 switches will be turned on I_out = kVref/R Inherently monotonic

9 Comparison Pros Cons R2R Simple Easy to extend resolution
Matching is poor MSB/LSB same variation Thermometer Inherently monotonic Balanced variation Large area Complex digital decoder (area)

10 Can combine thermometer code and binary ladder:

11 12-bit Hybrid R2R DAC Design
Segmentation NM-bit MSB + NL-bit LSB R2R: Each bit has 3R (2R+1R) An additional 2R 3*NL+2 Thermometer: (2NM -1)*2 MSB-ISB 4-8 5-7 6-6 MSB Area 30 62 126 LSB Area 26 23 20

12 12-bit Hybrid R2R DAC Design
Switch Ron needs to be small (simulate) Ron Mismatch Can use only NMOS

13 12-bit Hybrid R2R DAC Design
Clock Use DFF for Din Use clocked buffer CLK


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