1. Chapter 10
Combinational
Circuits

3. Boolean Algebra and Logic Gates
A circuit:
a collection of devices that are physically connected by wires.
The two basic types of circuits at Level LG1:
Combinational
Sequential.

4. Each line can carry a signal whose value is either 1 or 0.
Figure 10.2
Each line can carry a signal whose value is either 1 or 0.

5. Combinational circuit
The output depends only on the input
i.e. if you put in abc = 101 today and get out xy = 01, then if you put in abc = 101 tomorrow you will get out xy = 01 again
This behavior is not characteristic of a sequential circuit
It may be possible for you to put abc = 101 into a sequential circuit and get out xy = 01 at one moment, but xy = 11 a few microseconds later

6. Methods to describe a combinational circuit
Truth table
Boolean algebraic expression
Logic diagram

7. Truth table
Lists the output for every combination of the input

8. Figure 10.3

9. Figure 10.4

10. Boolean algebra Three basic operations Binary OR + Binary AND •
Unary Complement ´

11. Ten properties of boolean algebra
Commutative
Associative
Distributive
Identity
Complement

12. Commutative

13. Associative

14. Distributive

15. Identity

16. Complement

17. Figure 10.5

18. Distributive

19. Complement

20. Associativity

21. Duality To obtain the dual expression Exchange + and •

22. Example In the distributive property x + (y · z) = (x + y) · (x + z)
if you exchange the + and · operators, you get
x · (y + z) = (x · y) + (x · z)
which is the other distributive property.
Each fundamental property of Boolean algebra has a corresponding dual property.

23. Idempotent property

24. Zero theorem

25. Absorption property

26. Consensus theorem

27. De Morgan’s law

28. Complement theorems

29. QUESTION Find complement of the following Boolean expression:
F1 = x’yz’ + x’y’z

30. ANSWER F1 = x’yz’ + x’y’z The dual of F1 is (x’ + y + z’)(x’ + y’ + z)
Complement each literal:
F1’ = (x + y’ + z)(x + y + z’)

31. QUESTION Find complement of the following Boolean expression:
F2 = x(y’z’ + yz)

32. ANSWER F2 = x(y’z’ + yz) The dual of F2 is x + (y’+z’) .(y+z)

33. Logic diagrams An interconnection of logic gates
Closely resembles the hardware
Gate symbol represents a group of transistors and other electronic components
Lines connecting gate symbols represent wires

34. Figure 10.6

35. Figure 10.7

36. Figure 10.8

37. Figure 10.9

38. Figure 10.10

39. Set theory representation
OR gate is set union
AND gate is set intersection
Inverter is set complement

40. Figure 10.11

41. Figure 10.12

42. Boolean expressions and logic diagrams
AND gate corresponds to AND operation
OR gate corresponds to OR operation
Inverter corresponds to complement operation

43. QUESTION
Draw the logic diagram for the expression a + b.c’

44. Figure 10.13
ANSWER

45. QUESTION
Draw the logic diagram for the expression
((ab + bc’)a)’

46. Figure 10.14
ANSWER

47. Abbreviated logic diagrams
Any signal can be duplicated by a junction of two wires
The complement of any variable can be produced by an inverter

48. Abbreviated version of Figure 10.14

49. Figure 10.16

50. QUESTION
What is the Boolean expression of output F(A,B,C)
F(A,B,C)

51. ANSWER

52. Truth tables and boolean expressions
Given a truth table, write a boolean expression without parentheses as an OR of several AND terms
Each AND term corresponds to a 1 in the truth table

53. Figure 10.17

54. Figure 10.18

55. QUESTION
Show the behavior of the following circuit with a truth table:

56. ANSWER

57. QUESTION
Show the behavior of the following circuit with a truth table:

58. ANSWER

59. QUESTION
Derive truth table for Boolean expression for a′bd′ + a′c′d′.

60. ANSWER

61. Two-level circuits gate delay:
time it takes for the output of a gate to respond to a change in its input (~2ns)
Any combinational circuit can be transformed into an AND-OR circuit or an OR-AND circuit with at most two gate delays (not counting the gate delay of any inverters)
When you change a signal at the input of a gate, the output does not respond instantly. Instead, there is a time delay during which the signal works its way through the internal electronic components of the gate. The time it takes for the output of a gate to respond to a change in its input is called the gate delay.

62. AND- OR (Sum of Products - SOP)
QUESTION
Use Boolean logic rules to convert Boolean expression (a′bc ⊕ c + a + d)′ to AND-OR expression

63. ANSWER

64. Figure 10.19
AND- OR Expression
We used Boolean algebra to write the expression for this circuit as an AND-OR expression:
corresponding circuit: x
= (a′bc ⊕ c + a + d)′
= a′bd′ + a′c′d′
Alternatively, you can make what amounts to a truth table for the expression
two-level circuit because a change in the input requires only two gate delays to propagate to the output

65. Equivalent to circuit of Figure 10.17

66. Equivalent two level circuit
Three level circuit
Equivalent two level circuit

67. Question
Convert following expression into AND-OR(sum of products SOP) expression
(ac+b)(a+b’c)+ac

68. Answer
Then make sure that every term contains each of a,ba,b, and cc by using the fact that x+x’=1:

69. Alternatively, you can use a truth table to derive the SOP (AND-OR) expression:
ab’c
abc’
abc

70. OR-AND (Product of Sums POS)
x = (a + b′ + c′)(a′ + b′ + c):

71. two-level OR-AND circuit
x = (a + b′ + c′)(a′ + b′ + c)

72. Question
Convert following Boolean expression to OR-AND (POS) expression:

73. Answer
STEP1: Use De Morgan’s laws to negate (invert) the original expression

74. STEP2: Now find the SoP form of this:

75. STEP3: negate (invert) last expression, to get PoS form
You can use the truth table to get the PoS as well. This time you’ll use the rows in which the expression evaluates to 0

76. Using truth table: OR-AND (POS) term: a+b+c a+b+c’ a+b’+c a+b’+c’
a’+b+c
OR-AND (POS) term:

77. Question
Convert thisexpression: x = a + b′c to OR-AND terms

78. Answer
x = a + b'c first write its complement x’ x‘ = (a + b'c)' = a'(b'c)' = a'(b + c') = a'b + a'c’ (AND-OR) expression. Now use De Morgan’s law to write x as x = (x')' = (a'b + a'c')' = (a'b)'(a'c')' = (a + b')(a + c) (OR-AND) expression.
It usually happens that a circuit with three or more levels requires fewer gates than the equivalent two-level circuit. Because a gate occupies physical space in an integrated circuit, the two-level circuit achieves its faster processing time at the expense of the extra space required for the additional gates.

79. Simplifying Expressions
We use the following laws of Boolean algebra for simplifying expressions

80. QUESTION
Simplify following Boolean expression to minimal number of terms:
x + x’y

81. ANSWER
X + X’Y
= (X+X’)(X+Y)
= (1).(X+ Y)
= (X+Y)

82. QUESTION
Simplify following Boolean expression to minimal number of terms:
X(X’ + Y)

83. ANSWER
X(X’+Y)
=XX’ + XY
=0 + XY
= XY

84. QUESTION
Simplify following Boolean expression to minimal number of terms/literals:
XY + X’Z + YZ

85. ANSWER XY+X’Z+YZ = XY + X’Z + YZ(1) = XY + X’Z + YZ(X + X’)
=XY + X’Z + XYZ + X’YZ
= XY(1+Z) + X’Z (1+Y)
= XY + X’Z

86. Canonical expressions
A minterm(m) is a term in an AND-OR expression(product term) in which all input variables occur exactly once
e.g. xy
The four minterms for the two variables X and Y are X Y, X’Y, XY’, and X’Y’

87. QUESTION
How many minterms are possible for n variables?

88. ANSWER
2n -1

89. A Boolean function can be constructed from a given truth table
by forming the logical sum of all the minterms that produce a 1 in the function.
This expression is called a sum of minterms(A CANONICAL EXPRESSION) .

90. Figure 10.25

91. QUESTION
Express the Boolean function of following truth table as a sum of minterms:

92. ANSWER F = X’Y’Z’ + X’YZ’ + XY’Z + XYZ = m0 + m2 + m5 + m7 m0 m1 m2 m3

93. QUESTION
Express the Boolean function F = A + B’C in sum of minterms

94. ANSWER A: B’C: F(A,B,C) = A + BC’ A = A(B+B’) = AB + AB’
= AB(C+C’) + AB’(C+C’)
= ABC + ABC’ + AB’C + AB’C’
B’C:
B’C = B’C(A+A’) = AB’C + A’B’C
F(A,B,C) = A + BC’
= ABC + ABC’ + AB’C + AB’C’ + A’B’C
= m m m5 + m m1
= (1,4,5,6,7)

95. Another way .. F(A,B,C) = A + BC’ = ABC + ABC’ + AB’C + AB’C’ + A’B’Cm0 m1 m2 m3 m4 m5 m6 m7
F(A,B,C) = A + BC’
= ABC + ABC’ + AB’C + AB’C’ + A’B’C
= m m m5 + m m1
= (1,4,5,6,7)

96. Maxterm(M)
A sum term that contains all the variables in complemented or uncomplemented form
possible to formulate 2n maxterms with n variables.
Mj = mj’ and mj = Mj’
E.g. M3 = X+Y’+Z’ = (X’YZ)’ = m3’

98. Figure 10.25

99. QUESTION
Express the Boolean function F = xy + x’z in a product of maxterm form.

100. ANSWER
First, convert the function into OR terms using the distributive law:
The function has 3 variables, x,y,z. Each OR term is missing one variable.So:

101. Combining all the terms we get:

102. Conversion Between Canonical Terms
Consider the function expressed as a sum of minterms:
Complement F’:
F = (F’)’

103. Karnaugh maps Method for simplifying Boolean expressions
A Karnaugh map is a truth table arranged so that adjacent cells represent adjacent minterms
Two minterms are adjacent if the distance between them is one
The distance between two minterms is the number of places in which they differ

104. We will consider maps for two, three, and four variables
2-variable map
3-variable map
number of squares in each map is equal to the number of minterms m7
4-variable map

105. Figure 10.26

106. Two Variable Maps E.g. two variable function F(A,B):
STEP1: enter the function(truth table, sum of minterms) into map
E.g. two variable function F(A,B):
F = A’ + AB
F(A, B) = m(0, 1, 3)

107. STEP2: Identify rectangle of squares on the map for simplifying expression
Goal:
find the fewest such rectangles that cover all of the squares marked with 1s.
Rectangles of 1s should be large as possible
This will give the fewest product terms
A’B’ + A’B = A’
A’B + AB = B

108. STEP4: determine if any of the rectangles is not needed to cover all of the 1s on the K-map.
A rectangle can be deleted (not required) if all it’s are covered by the remaining rectangles.
If there are choices as to which rectangle of two having unequal size to remove, the largest one should remain.
Rectangle A’ needed to cover minterm 0
Rectangle B needed to cover minterm 3

109. + F = A’ + B STEP4: read off the sum-of-products (AND-OR) expression
A’B’ + A’B = A’ +
F = A’ + B
A’B + AB = B

110. QUESTION
Simplify the expression G(A, B) = m(1, 2) using Karnaugh Maps

111. ANSWER
G(A, B) = A’B + AB’

112. Three- Variable Maps

113. Figure 10.27

114. Figure 10.28

115. Figure 10.29

116. Decimal labels for the minterms
Figure 10.30
Decimal labels for the minterms

117. Figure 10.31

118. Figure 10.32

119. Figure 10.33

120. QUESTION Simplify the Boolean function:
F(A, B, C) = m(0, 1, 2, 3, 4, 5)
Using Karnaugh Maps

121. ANSWER A’
F = A’ + B’ B’

122. QUESTION Simplify the Boolean function G(A, B, C) = m(0, 2, 4, 5, 6)
Using Karnaugh maps

123. ANSWER
AB’ C’
F = C’ + AB’

124. QUESTION Simplify the Boolean function H(A, B, C) = m(1, 3, 4, 5, 6)
Using Karnaugh maps

125. One of Rectangle (1, 5) or (5, 4) can be deleted
ANSWER
One of Rectangle (1, 5) or (5, 4) can be deleted
A’C
AC’
F = A’C + AB’ + AC’
AB’
deleted

126. Four-Variable Map Simplification

127. Figure 10.34

128. Figure 10.35

129. Figure 10.36

130. Figure 10.37

131. Another correct minimization of Figure 10.37

132. QUESTION Simplify the Boolean function
F(A, B, C, D) = m(0, 1, 2, 4, 5, 6, 8, 9, 10, 12, 13)
Using Karnaugh maps

133. ANSWER
B’D’
F = A’D’ + B’D’ + C’
A’D’ C’

134. QUESTION Simplify the Boolean function
G(A, B, C, D) = A’C’D’ + A’D + B’C + C D + AB’D’
Using Karnaugh maps

135. G(A, B, C, D) = A’C’D’ + A’D + B’C + C D + AB’D’
ANSWER
G(A, B, C, D) = A’C’D’ + A’D + B’C + C D + AB’D’
A’D
A’C’D’
B’C CD
B’D’
A’C’
restructure
G = B’D’ + A’C’ + CD CD
AB’D’

136. Dual Karnaugh maps
To minimize a function in an OR-AND expression minimize the complement of the function in the AND-OR expression
Use x = (x´)´ and De Morgan’s law

137. Figure 10.29(c)
Figure 10.39

138. Don’t Care Conditions
The minterms of a Boolean function specify all combinations of variable values for which the function is equal to 1.
The function is assumed to be equal to 0 for the rest of the minterms.
This assumption, however, is not always valid, since there are applications in which the function is not specified for certain variable value combinations.

139. There are two cases in which this occurs:
input combinations never occur.
E.g. 4-bit binary code for the decimal digits has six combinations that are not used and not expected to occur.
input combinations are expected to occur, but we do not care what the outputs are
In both cases, the outputs are said to be unspecified for the input combinations.

140. Don’t-care conditions
A don’t care condition is shown as an X in a Karnaugh map
In choosing adjacent squares to simplify the function in a map, the don’t-care minterms may be used.

141. EXAMPLE incompletely specified function F
F has three don’t-care minterms d

142. Figure 10.40

143. NAND – Not AND NOR -Not OR
E.g. (abc)′
De Morgan’s law states that
(abc)′ = a′ + b′ + c′ (OR of inverted input)
NOR -Not OR
E.g. (a + b + c)’ = a’b’c’ (AND of inverted inputs)

144. Figure 10.21

145. you replace an arbitrary AND-OR circuit entirely with NAND gates

146. QUESTION
Convert the following AND-OR circuit to all NAND gate circuit (NAND-NAND circuit)

147. Figure 10.22 abc + def = ((abc + def)’)’ =((abc)’.(def)’)’
Last nand gate in (b)
Drawn as inverted input OR

148. Similarly you can create a NOT gate from NOR gate:
Figure 10.23
you can construct an inverter from a NAND gate by connecting the NAND inputs together
Similarly you can create a NOT gate from NOR gate:

149. NAND gates
Conceptually, you can construct any combinational circuit from only NAND gates.
Furthermore, NAND gates are usually easier to manufacture than either AND or OR gates.
Consequently, the NAND gate is by far the most common gate found in integrated circuits.

150. AND, OR and NOT Gates from NAND

151. Two graphic symbols for NAND Gate

152. NAND-NAND circuit from a Boolean expression

153. Example F = A + (B’ + C)(D’ + BE) AND-OR NAND with two graphic symbols
NAND with one graphic symbols

154. Another Example F = (CD + E)(A+B’) Introduce bubbles
Matching bubbles
Introduce bubbles
to make AND a NAND
and OR an NAND

155. NOR gates
The same reasoning that applies to NAND circuits also applies to NOR circuits.
Any combinational circuit can be written as a two- level OR-AND circuit, which can be written as NOR-NOR.
You can conceptually construct any combinational circuit with only NOR gates.

156. NOT, OR and AND Gates from NOR

157. Two graphic symbols for NOR Gate

158. Figure 10.24

159. Example

160. Combinational Devices
combinational devices that are commonly used in computer design

161. Enable lines
An enable line to a combinational device turns the device on or off
If enable = 0 :
the output is 0 regardless of any other inputs
If enable = 1:
the device performs its function with the output depending on the other inputs

162. Figure 10.41
Enable Gate
An AND gate can implement the enable property

163. Selective Inverter Gate
For input, it has a data line and an invert line.
If the invert line is 1:
the output is the complement of the data line.
If the invert line is 0:
the data passes through to the output unchanged.

164. selective inverter is an XOR gate
Figure 10.42
selective inverter is an XOR gate

165. Multiplexer
A multiplexer selects one of several data inputs to be routed to a single data output
Control lines determine the particular data input to be passed through

166. 2–to–1-line multiplexer
two information inputs, I0 and I1, and a single select input S
S = 0 output= I0
S = 1 output= I1

167. 4-to-1-line multiplexer
Y depends on four inputs I0, I1, I2, and I3 and two select inputs S1 and S0

168. The eight-input multiplexer
Figure 10.43
The eight-input multiplexer
2n input lines and n selection inputs

169. Figure 10.44

170. Binary decoder
A decoder takes a binary number as input and sets one of the data output lines to 1 and the rest to 0
The data line that is set to 1 depends on the value of the binary number that is input
An n-bit binary code can represent up to 2n distinct elements of coded information

171. The 1 x 2 binary decoder

172. Figure 10.45
The 2 x 4 binary decoder

173. A 2 x 4 binary decoder with enable
Figure 10.47
A 2 x 4 binary decoder with enable

174. QUESTION Design a BCD–to–Seven-Segment Decoder:
electronic products as alarm clocks often use light-emitting diodes (LEDs). Each digit is formed from seven LED segments.
A BCD(Bianry Coded Decimal)–to–seven-segment decoder accepts a decimal digit in BCD and generates the appropriate outputs for the segments of the display for that decimal digit. The seven outputs of the decoder (a, b, c, d, e, f, g)

175. ANSWER

176. Demultiplexer
A demultiplexer routes a single input value to one of several output lines
Control lines determine the data output line to which the input gets routed

177. The four-output demultiplexer
Figure 10.48
The four-output demultiplexer

179. Half adder
The half adder adds the right-most two bits of a binary number
Inputs: The two bits
Outputs: The sum bit and the carry bit

180. Figure 10.49
The half adder

181. Full adder The full adder adds one column of a binary number
Inputs: The two bits for that column and the carry bit from the previous column
Outputs: The sum bit and the carry bit for the next column

182. Figure 10.50
The full adder

183. Sum Cout Sum = A’B’Cin + A’BCin’ + AB’Cin’ + ABCin = A  B  Cin
Cout = AB + ACin + Bcin

184. Figure 10.51
If either the first or second half adder has a carry, the full adder has a carry out.

185. Ripple-carry adder
The ripple-carry adder adds two n-bit binary numbers
The full adders are connected in cascade, with the carry output from one full adder connected to the carry input of the next full adder.
Inputs: The two n-bit binary numbers to be added
Outputs: The n-bit sum, the C bit for the carry out, and the V bit for signed integer overflow

186. Figure 10.52

187. Q. Design a Gray code–to–BCD code converter that gives output code 1111 for all invalid input combinations. Assume that the Gray code sequence for decimal numbers 0 through 9 is 0000, 0001, 0011, 0010, 0110, 0111, 0101, 0100, 1100, and All other input combinations should be considered to be invalid
Answer:
Q. Design a circuit with a 4-bit BCD input A, B, C, D that produces an output W, X, Y, Z that is equal to the input + 3 in binary. For example, 9 (1001) + 3 (0011) = 12 (1100). The outputs for invalid BCD codes are don’t-cares.
Answer:

188. References
Logic & Computer Design Fundamentals, 5th Edition, By M. Morris R. Mano, Charles R. Kime, Tom Martin
Computer System Architecture, 3rd Edition, By M. Morris R. Mano