1. Basic Digital Logic Systems
Review
Basic Digital Logic Systems
Digital Design
Review

2. Outline Number Systems / Binary Encoding Boolean Algebra
Combinational Circuits
Sequential Circuits
Digital Design
Review

3. 1. Number Systems
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4. Positional Number System
For base-10 numbers:
289 = 2x x x100
Works for other bases
Base 6: (we indicate base explicitly) 2356 = 2x62 + 3x61 + 5x60
Fractional Numbers:
= 7x x x x x10-3
52.18 = 5x81 + 2x80 + 1x8-1 = /8 =
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5. Binary Numbers Digital Systems
Everything must be represented internally using {0,1}
Base 2 or “binary” = 1x23 + 1x21 + 1x20 = = 1110
Binary digits = “bits”
k-bit unsigned number represents values 0 to 2k-1
Convention:
Most significant bit (MSB)
Least significant bit (LSB)
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6. Conversion Between Bases
Like long division: Example: convert to base 6
112
(3x62) 4
(0x61) => 3046
(4x60)
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7. Conversion Between Bases
12.625
(1x23)
4.625
(1x22)
0.625
(0x21)
(0x20)
(1x2-1)
0.125
(0x2-2)
(1x2-3) =>
Other bases Example: convert to binary
Should be able to do this to understand meaning
In practice: use a calculator (except simple conversions)
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8. Hexadecimal
Base 16 is Hexadecimal (“Hex” for short)
Run out of numbers for digits, so use letters
For example 1A2F16 = 1x x x x160 =
Why are hex numbers useful? Shorthand for binary.
Going back and forth equally easy
Worthwhile to memorize hex digits and binary equivalents
Hex 1 2 3 4 5 6 7 8 9 A B C D E F
Dec Equiv. 10 11 12 13 14 15
0000|1010|0110| binary
0 A hex
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9. Other Codes Binary Coded Decimal (BCD) Gray Codes ASCII
Single decimal digit maps to 4 bits
Simplifies display / conversion of decimal numbers
Example: = BCD
More bits needed, but it is still often useful
Gray Codes
Adjacent numbers differ only by one bit
ASCII
“American Standard Code for Information Interchange”
7-bit code for alphabet and some control characters ‘A’ = 4116 or 6510, ‘.’ = 2E
Decimal
Gray
000 1
001 2
011 3
010 4
110 5
111 6
101 7
100
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10. Unsigned Arithmetic
Addition of unsigned (non-negative) of any base can be done with “elementary school” method
Add 2 binary numbers, just need simple rules
0+0+0=00, 0+0+1=01, 0+1+1=10, 1+1+1=11 C = “carry” bit
Addition of two k-bit numbers Can lead to k+1 bit number
Carry in the left-most position means “overflow” has occurred 1
1 1 1
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11. Signed Magnitude How do we represent negative numbers?
How about usual thing with written numbers?
Use one bit to mean + (0) or – (1)
Digital systems: called the “sign” bit
Example:
+310 =+ (0112) = 0011SM
-310 =- (0112) = 1011SM
Advantages: Simple. Sign and number separate
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12. Signed Magnitude Disadvantages Two representations of 0
Arithmetic more complicated
Arithmetic with signed magnitude
5 + (-2) = 5 – 2 = 3
5 – (-2) = = 7
-5 – 1 = - (5 + 1) = -6
Must consider signs and do add/sub accordingly
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13. 2s Complement
Use the usual positional notation, but we invert sign of leftmost weight
Note: MSB can still be considered a “sign” bit indicating if number is + or –
For + number, remaining bits can be interpreted as unsigned number
11112C = -1x23 + 1x22 + 1x21 + 1x20
= = -110
10112C = -1x23 + 0x22 + 1x21 + 1x20
= = -510
01112C = -0x23 + 1x22 + 1x21 + 1x20
= = +710
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14. 2s Comp: Sign Extension
How do we make 2’s complement number longer? (maybe need more bits)
Answer: duplicate the sign bit.
00112C = C = C = 310
10112C = C = C = -510
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15. 2s Comp: Negating How do we flip the sign of a 2s complement number?
With signed magnitude: just flip bit.
For 2s complement, invert all bits and add 1 (use modulo unsigned arithmetic)
Why does this last conversion fail?
+510 = 01012C =>(inv)=> = 10112C = -510
-510 = 10112C =>(inv)=> = 01012C = -510
+0 = 00002C =>(inv)=> = 00002C = 0
-810 = 10002C =>(inv)=> = 10002C = !?
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16. 2s Comp: Addition This is the main advantage of 2s complement
Just do normal arithmetic (regardless of sign bit)
We can also have overflow when we add 2s complement numbers.
How do we detect it?
Only possible for same sign. Check sign bit, if it changes => overflow.
How do we avoid it?
Sign extend, then add
1 1 1
1 1 1
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17. 2. Boolean Algebra
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18. Boolean Algebra Named after George Boole in 19th century
Map: TRUE  1, FALSE  0
Operators: AND a·b or just ab OR a+b NOT a’ or a
DeMorgan’s (DM) Rules
(AB)’ = A’ + B’
(A+B)’ = A’B’
Easily proven using a truth table ...
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19. Truth Tables Simple 2-variable truth tables
Can obviously extend to more than 2 input variables (output variables) A B F 1 A B F 1 A B F 1 A B F 1
A=B
F=1 OR
F=AB’
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20. Truth Tables  Boolean Alg.
Sum of Products (SOP) form
OR the true rows in the truth table
F = A’B + A B’ A B F 1
A’B’
A’B
AB’ AB
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21. Truth Tables  Boolean Alg.
Product of Sums (POS) form
AND the false rows in the truth table
F’ = A’B’ + AB
F’ = [(A’B’)’ (AB)’]’ (DM)
F = (A+B) (A’ + B’) (DM) A B F 1
A’B’
A’B
AB’ AB
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22. Boolean Eq.  Truth Table
Repeatedly evaluate expression for all combinations.
Can be more efficient to fill just TRUE terms F = A’B + A B
F = A + A’B
A’B AB A B F 1
A’B A A B F 1
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23. Boolean Identities Single Variable
Two Variable useful for reducing # of terms on complex exp. Simplification Theorems Consensus Theorem difficult to find opportunities to use cons. thm.
A · 0 = 0
A · 1 = A
A + 0 = A
A + 1 = 1
A · A’ = 0
A + A’ = 1
A · A = A
A + A = A
A + A’B = A + B
A(A’ + B) = AB
AB’ + AB = A
(A+B’)(A+B) = A
AC + A’B + BC = AC + A’B
Redundant
(A+C)(A’+B)(B+C) = (A+C)(A’+B)
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24. Boolean Identities (cont’d)
Communitive, Associative, Distributive Thms
AB = BA A+B=B+A Communitive
(AB)C = A(BC) (A+B)+C = A+(B+C) Associative
A(B+C)=AB + AC Distributive
A+BC = (A+B)(A+C) Distributive
Duality: For a valid equality, its “dual” is also true Dual: Replace AND ↔ OR ↔ 0 Example: A(B+C) = AB + AC know this is valid, then A + BC = (A+B)(A+C) Note: An expression is not equivalent to its dual! Be careful of precedence.
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25. Canonical Forms Purpose SOP form “minterm” expansion
Means: “Write a an expression in most standard way.”
Trivial to tell if two expressions are identical
SOP form “minterm” expansion
“minterm” = product term having all variables A B F 1 m0 m1 m2 m3
F = A’B’ + A’B + AB = m0 + m1 + m3 = ∑m(0,1,3)
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26. Canonical Forms POS form “maxterm” expansion A B F 1 M0 M1 M2 M31 M0 M1 M2 M3
F = (A’ + B)(A’ + B’) = M2 · M3 = π M(2,3)
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27. Proving Boolean Expressions
Methods
Truth table
Minterm/maxterm expansion (same terms?)
Manipulate one side to = other (identities)
Manipulate both sides with identical operations
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28. Boolean Minimization
Make expression as “simple” as possible (low number of terms)
AB’ = AB = A(B’ +B) = A· 1 = A
Less complicated expression  Fewer gates, less area, runs faster
Attempt to find minimal cost solution
What is minimal representation? Depends on technology and contraints.
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29. Boolean Minimization Example technologies MSI - 7400
Min. chip count One type of gate preferable
NMOS
NOR gates
Literal count
(count # of terms)
*CMOS
NAND gates
FPGA
Minimum number of
Lookup Tables (LUTs)
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30. Incompletely Specified FuncsA B C F X Y Z W A B C F 1 X
Suppose we know N1 will never generate 101 or 111
Can pick don’t cares to help minimize logic.
“Don’t cares”
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31. K-Maps Karnaugh Map (K-Map for short)
Graphical way of obtaining minimal solutions
Take advantage of logical adjacency to reduce exp.
Consider: F = A’B’ + A’B = A’ From simplification theorem AB’ + AB = A
Terms A’B’ and A’B are adjacent in gray code (differ by 1 bit)
See adj. terms  Immediately use simp. thm.
F = ABCD + AB’CD = ACD A B F 1
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32. K-Maps (cont’d) 2 Variable Rearrange truth table (gray code) B A
K-map more compact (can see adjacent bits) A B F 1 A B F 1
F = B
F = B
B A 1
F = A’B + AB = B
Can write F=B from K-map without using simplification theorem
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33. K-Maps (cont’d)
Minterm (SOP) Method - Draw rectangles (ovals) to group as many 1s as possible. - Repeat until all 1s circled - Now OR the resulting terms (1 per oval) A B F 1
B A 1
F = B A B F 1
B A 1
F = A + B
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34. K-Maps: Don’t cares Can put X’s (don’t cares) in K-map
What do we do with them?
Doesn’t matter! We can circle them or not, in order to have as few terms (biggest ovals) as possible.
B A 1 X
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35. K-Maps: 3 Variable BCA BCA BCA 1 0 0 m0 m4 0 1 m1 m5 1 1 m3 m7 1 0 m21
0 0 m0 m4
0 1 m1 m5
1 1 m3 m7
1 0 m2 m6
BCA 1
0 0 X
0 1
1 1
1 0
X = 0  F = A’C + BC A B C F X 1
BCA 1
0 0 X
0 1
1 1
1 0
Exploit don’t cares  F = C
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36. 3. Combinational Circuits
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37. Combinational Logic Definition Outputs depend only on inputs
No “memory” or “state”
Can have propagation delay
But, eventually output determined by simple Boolean algebra
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38. Gates Logic Gates (or just “gates”) Goal
Basic building block in digital systems
Goal
Review different types of gates
Understand how to connect to get desired (arbitrary) Boolean expression
Define performance (delay)
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39. Basic Gate Notation A B F A A F NOT: F=A’ F B AND: F=AB OR: F=A+B
Example: F=AB’ + C A B F C
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40. Gates from Transistors
Gates Come from FETs
n-Type FET
p-Type FET D D
Drain
+3V 0V
Gate G
“on” G
“off”
Source S S D D
Drain
+3V 0V
Gate G G
“off”
“on”
Source S S
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41. Inverter (NOT Gate)
Vcc=3V
Vin
Vout
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42. Inverter (NOT Gate) Vcc=3V Vcc=3V 3V ON OFF 0V OFF ON 3V 0V
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43. NAND Gate
Vcc
F = (AB)’ A B A B F 1 F A B
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44. NAND Gate F=(AB)’ Vcc Vcc off on 1 1 1 1 A off on B A B F F 1 1 A A 1A
off on B A B F F 1 1 A A 1 B B
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45. AND Gate? Does this work? Limitations Why? Not really. nFETs pass 0
Vcc
Does this work?
Not really.
Limitations
nFETs pass 0
pFETs pass 1
Why?
Operation depends on Vgs (not just Vg) 1 A on 1 B on F A
off B
off
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46. NOR Gate F = (A+B)’ A B F 1 Vcc A on B on 1 F A off B offA on A B F 1 B on 1 F A
off B
off
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47. Analysis/Synth. Rules nType can pass “0” pType can pass “1”
For all input combinations output must be connected to VCC or GND (Not both, and not floating)
For logic with both p- and n-type FETs p-type stack (pull up) n-type stack (pull down) n- and p- stacks are complimentary (series/parallel)
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48. Other Gates XNOR (Equiv.) XOR A B F=(A==B) 1 A B F=AB 1 A A F F B B A1 A B
F=AB 1 A A F F B B A
Uses: Parity check (odd  1) Adder circuits Bit flipping = F B
Parity check (even  1)
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49. Functionally Complete Logic
Definition
Set of gates that can be used to realize all logic functions
Minimal set
Just one gate
NAND
NOR
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50. Multi-Input Gates Extend gates by adding inputs Problem?
Larger propagation delay due to series connected FETs.
Increase speed with higher current (larger area)
Gate width tradeoff: area, speed, power
4-input NAND
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51. Bubbles Alternate Gate Representations Choice can indicate meaning
Location of bubble: Are we concerned about TRUE or FALSE values?
(a) Output is FALSE when one input is TRUE (b) Output is TRUE when both inputs FALSE A A B F
NOR F B
(a) F=(A+B)’
(b) F=A’B’
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52. Positive/Negative Logic
Alternative Interpretation
Positive Logic (no bubble) 1 = asserted (TRUE) 0 = negated (FALSE)
Negative Logic (bubble) 0 = asserted (TRUE) 1 = negated (FALSE)
(a) OR gate with + input and – output (b) AND gate with – input and + output A A B F F B
(a) F=(A+B)’
(b) F=A’B’
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53. Examples
AND OR
NOT
Mixed
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54. Which do you use? Consider readability
What are you trying to describe?
TRUE when all inputs FALSE
FALSE when any input TRUE
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55. Bubble Matching Good convention Helps with readability
Nice, we can mentally cancel bubbles
Immediately see logic A A B F B F C C D D
F=((AB)’(C+D)’)’
F=AB + C + D
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56. 2-Level Logic Can do any logic with 2 levels
AND  OR (SOP) OR  AND (POS)
Main advantage: Speed A B
G=AB + ACDE + ACF A C G D E A C F
tprop= tAND + tOR
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57. Multi-Level Logic Alternate: Multi-level Which is better? A B A C G
G=AB + ACDE + ACF D E A C F D
G=A[B+C(DE+F)] E F C B G A
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58. Multi-Level Logic Which is better depends
Speed: Worst-case delay Example: 2-level (2T), multi-level (5T)
Area: # of transistors (most precise) Gate count (approximate) 2-inp. NAND (4 trans) 3-input (6 trans) 2-level (12N), multi-level (10N)
Tradeoff: “Best” depends on
Technology
Speed/size/area requirements
General: 2-level (fast, big) multi-level (slow, small)
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59. Hardware Adders Full adder (1 bit) “Add up number of 1s”
How implemented?
Half adder:  a lot less logic! Where useful: Incrementer a b
cin s
cout 1
cout + s b
cin a
s = a  b  cin
cout = a b + b cin + a cin
s = a  b cout = a b
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60. Adder/Subtracter Module
add/sub’ + + + + a3 a2 a1 a0 b3 b2 b1 b0
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61. Multiplexers S chooses which input gets routed to output. S F A 1 B A1 A S F A 1 B F B 1 S
2:1 MUX
F = S’A + SB
S chooses which input gets routed to output.
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62. F = S1’S0’A + S1’S0B + S1S0’C + S1S0D
Larger MUXs S1 S0 F A 1 B C D A 00 B 01 F C 10 D 11 S1 S0
4:1 MUX
F = S1’S0’A + S1’S0B + S1S0’C + S1S0D
Can just keep following pattern...
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63. Larger MUXs Can form by cascading smaller MUXs A A 00 B 1 B 01 F C 10A 00 B 1 B 01 F C 10 D 11 F S0 1 C S1 S0 S1 D 1 S0
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64. Multi-bit Wires Routing multi-bit signals (busses)
Don’t want to draw all those wires!
Name: 4-input 2:1 MUX A 4 F B 4 1 4 S
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65. Decoder 2:4 Decoder “decodes” binary input valueF0 F1 F2 F3 I1 I0 F0 F1 F2 F3 1
2:4 Decoder
“decodes” binary input value
Min term generator Tells index of minterm presented at input
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66. Decoder Uses
Code Op 00
pass 01
add 10
and 11
not
Select which function (unit) is enable e.g. in a Arithmetic Logic Unit
Logic functions (just OR min terms) I1 I0 F0 F1 F2 F3 A
F(A,B) = ∑m(0,3) B
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67. Using MUXs, Decoders Making everything out of low-level gates
Highest degree of control over design
But may be difficult to read
Higher level MUXs, Decoders
Easier to read, understand function
Simpler to maintain design
Most CAD tools good at optimizing mapping of MUXs/Decoders to gates for given target technology
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68. ROMs Implement “random” logic Same as a look-up table (LUT)
Addr
Data 1 2 3 4 5 6 7
8x1 ROM A’ I2 B’ Q
Address I1 Q I0 A C’
Implement “random” logic
Same as a look-up table (LUT)
Used extensively in FPGAs
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69. Basic Delay in Gates Definitions
tprop,fall
Vin
tprop,rise
Vout
trise
tfall t
Definitions
tprop,fall / tprop,rise: 50% swing to 50% swing
trise: 10% to 90% tfall: 90% to 10%
Want to know: “how fast will design run”
Note that trise tfall and tprop,rise  tprop,fall
Usually consider: worst prop. delay Also, not worry about rise/fall
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70. Critical Path Analysis
“How fast will this run?” B A C Q D E F
Critical path
If we change input, how long before output has correct result?
Example: responds to A much faster than D
Want to know longest time or critical path
Not all gates equal: add up delay different gates / different technologies
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71. Input “glitches” Which happens? Depends: Technology
could be t B F ? or
Which happens?
Depends:
Technology
How narrow pulse is relative to tprop, trise, tfall
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72. Glitches (Transients)B C A F
Consider:
What is the output?
For static inputs: F=AA’=0
Single rising edge on A
Pulse generator?
Point: Inputs to comb. logic change  Transient period outputs fluctuate before final stable value A B C F
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73. Hazards/False Outputs
Definition
Output takes on a value that is not predicted by the Boolean expression for either old or new inputs
Dealing with Hazards
Circuits where only a single input changes at a time
Include redundant terms (in k-map)
Can eliminate hazards
Synchronous design
Signals only sampled on clock
Period made long enough to be past transients
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74. Variations in Gate Delays
Gate delay variation due to
Temperature
Vcc changes (imperfect power supply)
Process variations
Loading of gate
vs.
fast
slow
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75. 4. Sequential Circuits
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76. Complex Algorithms Require Digital Memory Elements
Series of operations to be performed
Order, timing important
Storage for intermediate results
Means we have memory
Digital Memory Elements
Latches
Flip-flops
SRAM, DRAM
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77. SR Latch Memory requires feedback Circuit has two stable states
Can control with R/S inputs R Q Q’ S
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78. SR Latch To see stability... Can repeat for Q=1 and Q’=0. Same thing.R Q Q’ S 1 1
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79. SR Latch
“Set” Operation. 1 1 R Q Q’ S 1 1 1
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80. SR Latch
“Reset” Operation. 1 1 1 R Q Q’ S 1 1
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81. SR Latch Transition Table R S Qnext Q 1 Undefined R Q Q’ S R Q S Q’Q 1
Undefined R Q Q’ S R Q S Q’
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82. SR Latch Summary Features Problems? Provides 1 bit of memory
Control by temporarily raising S or R
Problems?
Output can change at any time when S/R change Think about glitches!
Inconvenient to have two inputs to control How do we store just the bit on a line?
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83. Gated Latch Circuit responds when Gate=1Q R Q S Q’ S Q’ G S
Gate
Circuit responds when Gate=1
Sometimes called a “transparent latch” or a “lodable latch”
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84. D-Latch Stores value on input D when G is highQ D Q S Q’ Q’ G
Gate
Stores value on input D when G is high
Keeps old value otherwise
Now we can store a value, just when we want
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85. Using Latches Any problems? Level sensitive
Consider “toggle” circuit Output: 10 or 10 each time we assert Gate
Will this work? Q D G
Gate F
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86. Toggle Circuit Timing Circuit oscillates  BadQ D G
Gate F
Gate D F
Circuit oscillates  Bad
Feedback with gated latch is difficult
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87. Master/Slave Flip Flops
Idea
Use two latches to get “edge” sensitive behavior
Master
Slave Q1 D Q D Q D Q G G
clk D Q
Edge sensitive latch called a “flip flop”
clk
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88. Flip Flop Operation (1) When clk=1, only first latch is transparentQ D G Q1
Master
Slave
clk 1 1 1
When clk=1, only first latch is transparent
Transitions on D only go through first latch!
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89. Flip Flop Operation (2) Consider storing a 1 in the flip flopQ D G Q1
Master
Slave
clk 1 1 1 1 1
Consider storing a 1 in the flip flop
The bit got stored and sent to the output on a falling edge of clk (1=>0)
Kind of like an “airlock”
Make rising edge device with another inverter
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90. Utility of Flip Flops Example toggle circuit:
Q  D only on 01 transition of clk
Oscillation does not occur
Can store 1 bit, sampled at an edge Q D
clk F
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91. Flip Flop Timing D Q
clk
tsetup
thold
tclk-q
(a) tclk-a Time until new latched value appears at output
(b) tsetup Time before clock that D must be stable
(c) thold Time after clock that D must be stable
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92. Flip Flop Timing: tclk-qD Q Q’
Extra inverter makes + edge sensitive.
clk
(a) tclk-q : Time for new output to appear on Q
Gate gets to slave, value propagates through
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93. Flip Flop Timing: tsetupD Q Q’
clk
(b) tsetup: Time D must be stable before clock
Slave becomes transparent. Correct value must be at input!
Time to go through master stage.
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94. Flip Flop Timing: tholdQ Q’
clk
(c) thold: Time D must be stable after clock
Master latches. Should be value there at clock.
Time to lower gate on master.
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95. Registers Definition Example Storage element One or more flip flops
Four D flip flops in parallel: 4 4 D Q
clk
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96. Types of Registers (1) Loadable Register
Standard flip flop (or register) loads on every clock
May want to selectively load input
One idea:
Problems?
Adds delay to clock “clock skew”
What about glitches? Q D
clk EN
CLK
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97. Types of Registers (2) Loadable Register Better way Q D CLK EN 1 EN Q1 EN Q D
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98. Types of Registers (3) Shift Register Uses?
Extensions: Enable, Direction, Parallel Load, Clear, ... Q D
Sin Q0 Q1 Q2 Q3
CLK
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99. Counters Implementation Synchronous circuit made from a register
Steps up or down on each clock edge
Input (next value) computed from output (current value)
+1 block from half adders Q D
CLK +1
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100. State Memory (register)
Synchronous Circuits
General synchronous circuit
Counter
State Machine Q D
Input Forming Logic
Next State
State Memory (register)
Comb. Logic
Current State
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101. Synchronous Circuit Design
Designing a General Counter
State transition table Current state  Next state
Boolean eq. for next_state = F(curr_state)
Place flip flops between D Q F NS CS
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102. Generalization of Sync. Circuit
Finite State Machine (FSM)
Can be used to realize general sequential algorithms
Moore outputs (depend only on state)
Mealy outputs (depend on state and inputs)
Current State Q D
Input Forming Logic
Next State
Output Forming Logic
Inputs
Outputs
For Mealy Outputs
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103. Generalization of Sync. Circuit
Finite State Machine (FSM)
Input Forming Logic Q D
Output Forming Logic
Outputs
Next State
Current State
Inputs
For Mealy Outputs
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104. FSM Design Process Similar to Counter
Input Forming Logic Q D
Output Forming Logic
Outputs
Next State
Current State
Inputs
For Mealy Outputs
Process Similar to Counter
Write state transition table Implement using comb. logic
Write truth-table or Boolean eq. for output logic
Insert registers
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105. State Graphs Graphical representation of a state transition table
Helps you visualize FSM operation
Value in state register
Current State
Next State 00 01 10 11 Q1 Q0 N1 N0 1
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106. Inputs Represented with labels (signal name) on arc
Means if sig=1, take the path (arc)
clr
inc’ 00
inc
inc
clr
inc’
clr
inc’ 01 11
clr
inc
inc 10
inc’
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107. Proper State Graphs Conflict-free State Graph Complete State Graph
Only one possible next state for all possible inputs
Is previous counter with inputs conflict free?
Solve by introducing priority.
Complete State Graph
All next states are specified.
“Incomplete” means we have omitted some cases
inc 10 11
What happens when inc=‘0’ in 10?
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108. Outputs Put names of asserted signals next to (or in) state bubbles
A / MID 00 01 10 11
TERM
Means MID=1 in state 01 when A is asserted
“Mealy output”
Means signal TERM=1 in state 11 (0 otherwise)
“Moore output”
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109. Example Sequence recognizer “011” (Moore) Xin S0 X’in Xin Xin
Seq. Rec.
clk
X’in Z S1
X’in Z S3
X’in
Xin
Xin S2
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110. Example Sequence recognizer “011” (Mealy) Xin S0 X’in Xin Seq. Rec.
clk
Xin/Z Z S1
X’in
X’in
Xin S2
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111. One-Hot State Machines
Definition
More than one state, multiple flip flops for state
“One hot” means only one flip flop active (stores a 1) at a time
Uses?
Simpler to design by hand Finding next state logic tedious for very many states
Can eliminate output glitches
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112. One Hot Example go’ State transition table A go stop / Y run’ stop’ BCS NS X Y A 1 B go
run
stop CS NS X Y go
run
stop CS NS X Y A 1 B C D go
run
stop CS NS X Y A 1 B C D go
run
stop CS NS X Y A 1 B C A go
stop / Y
run’
stop’ B D X
run C
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113. One Hot Example A go’ D stop A Q D State transition table A go B run’CS NS X Y - A 1 B C D B Q D X B
run C Q D C D
stop’ D Q D
stop Y
Dns = Ccs + Dcs stop’
Ans = Acs go’ + Dcs stop
Bns = Acs go + Bcs run’
Cns = Bcs run
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114. One Hot Example Glitches? Mealy output Y Can have glitch
go’ D
stop A
Glitches?
Mealy output Y Can have glitch
Moore output FF does single trans. from CS to NS No glitch Q D A go B
run’ B Q D X B
run C Q D C D
stop’ D Y Q D
stop Y
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115. Summary Number Systems / Binary Encoding Boolean Algebra
Combinational Circuits
Sequential Circuits
Fundamental concepts and terms we need for the rest of the course.
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