1. Capacitance variation 3/ (%)
Performance and Variability Driven Guidelines for BEOL Layout Decomposition with LELE Double Patterning
Tuck-Boon Chan†
Andrew B. Kahng†‡
ECE† & CSE‡ Depts.,
UC San Diego
MOTIVATION
Resist
Patterning variations in LELE double patterning lithography (DPL)
Different stitching locations are
possible for double patterning
Hardmask
Questions:
Metal
1st Exp. & Etch
Can LELE pattern stitching strategy reduce on-chip timing variability?
What is the “best-practice” for choosing stitching location?
Is redundant stitching better?
stitches
1) Overlay
2) Independent exposures
1st Exp.
2nd Exp.
Interconnect spacing variation
2nd Exp.
Uncorrelated critical dimension (CD) variation
1st Exp.
2nd Exp.
2nd Etch
Final patterns
BIMODALITY IN DPL
RC VARIATION ANALYSIS
Study three interconnect patterns
Derive analytical equations for interconnect RC
Use 45nm (commercial) and 22nm (ITRS) parameters to calculate interconnect RC values
Ground plane Cs Cc H SL W2
neighbors T SR
victim
Color 1
Color 2 W1
DPL prints layout shapes in two exposures  Uncorrelated CD distribution  Different-color interconnects have uncorrelated RC distribution
(a)
Capacitance variation 3/ (%)
3 lines symmetric
Ground plane Cs Cc SL
neighbors SR
victim
(b)
1) Interconnect has less RC variation with uncorrelated RC distribution than with correlated RC distribution due to averaging effect
2) Stitching on long/critical interconnect  uncorrelated RC values  less timing variability
3 lines asymmetric
1) Pattern interconnect using DPL reduces capacitance variation by 20% (from 23% to 17%) compared to single patterning lithography (SPL) Redundant stitching reduces variability
2) Capacitance variation of symmetric case is 15% (from 20% to 17%) less than the asymmetric case
Ground plane Cs Cc SL
neighbor
victim Y X
(c)
2 lines
STITCHING IMPACT ON RC
STITCHING IMPACT ON DELAY
Calculate capacitance at different stitching locations using 45nm commercial parameters
Assign RC module before stitch location to Color 1 and after stitching location to Color 2
Simulate circuit delay using 22nm (predictive technology) and 45nm (commercial) HSPICE models
delay
stitching location
Color 1 length : x1
Stitching location
interconnect length
Color 2 length : x2
Color 1
Color 1
Color 2
Color 2
driver
receiver
20 RC modules
45nm technology
22nm technology
3 lines SPL
3 lines DPL
3 lines DPL asym.
2 lines SPL
2 lines DPL
CONCLUSIONS
3 lines SPL
2 lines SPL
3 lines DPL symmetric
2 lines DPL
Optimizing stitching location in DPL reduces 3 delay variation by 25% (from 20% to 15%)
Optimal stitching location is at midpoint along an interconnect but slightly shifted toward driver’s side due to resistance shielding effect
3/ capacitance (%)
3 lines DPL Asymmetric
3/ capacitance (%)
midpoint
midpoint
x1/(x1 +x2) (%)
x1/(x1 +x2) (%)
Optimal stitching location shifts to the driver side due to resistance shielding
Similar trends for 45nm and 22nm
Stitching at midpoint minimizes RC variation
No difference between asym. and sym. DPL at midpoint