1. Programmable Logic Devices

2. Programmable Logic Devices
The Process
Text Source File
Compiler
JEDEC Data File
Programmer
List
File
*JEDEC : Joint Electronic Devices Engineering Council

3. Programmable Language Devices
PAL : Programmable Array Logic
PLA : Programmable Logic Array
GAL : Generic Array Logic
PLD : Programmable Language Devices

4. 22V10 – Pin Diagram 22 V10 Optional Clock +5 Volts 22 Inputs
10 Variable Outputs 22
V10
Ground

5. 22V10 Functional Logic Diagram

6. 22V10 Functional Logic Diagram

7. OR / AND Logic Section

8. AND Array Prior To Programming
Inputs
Outputs
Fuses

9. AND Array After Programming
Where the fuse is left, the input is being used.
Where the fuse is intact, the input is being used.
Simplification is not necessary with PLDs

10. Macro Cell Section

11. Macro Cell Configurations (12)

12. Macro Cell Configurations (1-4)

13. Macro Cell Configurations (5-8)

14. Macro Cell Configurations (9-12)

15. PLD Languages CUPL – Universal Compiler for Programmable Logic
ABEL – Advanced Boolean Expression Language
Palasm – Sorry No Acronym Here

16. Two Design Approaches…
The Old Way…
Create Truth Table
Simplify Boolean Equation (K-Map or Boolean Algebra)
Design Logic Circuit
Test/Debug Circuit
Repeat steps 2, 3, & 4 as needed
The New Way…
Create Truth Table
Write Boolean Equation
Program PLD
Test/Debug Circuit
Repeat steps 2, 3, & 4 as needed

17. Design Example
Hex – 7 Seg Display B3 B2 B1 B0 a b c d e f g

18. The Old Approach.. Create Truth Table Simplify Boolean Equation
(K-Map or Boolean Algebra)
Design Logic Circuit
Test/Debug Circuit
Repeat steps 2, 3, & 4 as needed

19. HEX-To-Seven Segment Truth Table
Step 1. Create Truth Table
HEX Input
Seven Segment Display Output B3 B2 B1 B0 # a b c d e f g 1 2 3 4 5 6 7 8 9 A B C D E F

20. Segment ‘a’ – K Map & Equations
Step 2. Simplify Boolean Equations
__ __
B3 B2 __
B1 B0 1

21. Segment ‘b’ – K Map & Equations
Step 2. Simplify Boolean Equations
__ __
B3 B2 __
B1 B0 1

22. Segments ‘a’ – ‘g’
Step 2. Simplify Boolean Equations

23. Step 3. Design Logic Circuit
Step 4. Test / Debug
CircuitMaker 2000
HEX – 7 Seg Display
Step 5. Repeat Steps 2, 3, & 4
Not Needed… This Time

24. The New Approach.. Create Truth Table (same) Write Boolean Equation
Program PLD
Test/Debug Circuit
Repeat steps 2, 3, & 4 as needed

25. HEX-To-Seven Segment Truth Table
Step 1. Create Truth Table (same)
HEX Input
Seven Segment Display Output B3 B2 B1 B0 # a b c d e f g 1 2 3 4 5 6 7 8 9 A B C D E F

26. Segments ‘a’ – ‘g’ Step 2. Write Boolean Equations NO SIMPLIFICATION !
d = !b3 & !b2 & !b1 & b0 # !b3 & b2 & !b1 & !b0 # !b3 & b2 & b1 & b0 # b3 & !b2 & !b1 & b0 # b3 & !b2 & b1 & !b0 # b3 & b2 & b1 & b0;
e = !b3 & !b2 & !b1 & b0 # !b3 & !b2 & b1 & b0 # !b3 & b2 & !b1 & !b0 # !b3 & b2 & !b1 & b0 # !b3 & b2 & b1 & b0 # b3 & !b2 & !b1 & b0; f = !b3 & !b2 & !b1 & b0 # !b3 & !b2 & b1 & !b0 # !b3 & !b2 & b1 & b0 # !b3 & b2 & b1 & b0 # b3 & b2 & !b1 & b0; g = !b3 & !b2 & !b1 & !b0 # !b3 & !b2 & !b1 & b0 # !b3 & b2 & b1 & b0 # b3 & b2 & !b1 & !b0;
Step 2. Write Boolean Equations
NO SIMPLIFICATION !
a = !b3 & !b2 & !b1 & b0 # !b3 & b2 & !b1 & !b0 # b3 & !b2 & b1 & b0 # b3 & b2 & !b1 & b0; b = !b3 & b2 & !b1 & b0 # !b3 & b2 & b1 & !b0 # b3 & !b2 & b1 & b0 # b3 & b2 & !b1 & !b0 # b3 & b2 & b1 & !b0 # b3 & b2 & b1 & b0; c = !b3 & !b2 & b1 & !b0 # b3 & b2 & !b1 & !b0 # b3 & b2 & b1 & !b0 # b3 & b2 & b1 & b0;

27. Program & Test Step 3. Program PLD WinCUPL HEX – 7 Seg Display
Text Source File
Compiler
JEDEC Data File
Programmer
List
File
WinCUPL
HEX – 7 Seg Display
Step 4. Test / Debug
Step 5. Repeat Steps 2, 3, & 4
Not Needed… This Time

28. Comparison of Two Design Approaches
The New Way…
Less Effort
Easy To Change/Correct
Part Inventory
22v10 1 IC Total
1 x $ 3.50 = $ 3.50
The Old Way…
Greater Effort
Harder To Change/Correct
Part Inventory
Inverters (6) 1 IC
3 Input OR (3) 1 IC
4 Input OR (4) 4 ICs
3 Input AND (14) 5 ICs
4 Input AND (11) 6 ICs
17 x 50 ¢ = $ ICs