1. Possible Upgrades ToF readout Trigger Forward tracking
Alessandro Bravar

2. Mu3e @ PSI Lepton Flavor Violation in m ® e e e
Sensitivity ~10-16 (PeV scale !)
® observe ~1017 m decays
rate ~ 2 ´ 109 m decays / sec
200 M HV-MAPS (Si pixels w/ embedded ampli) channels
10 k ToF channels

3. The ToF Tracker 3000 Sci-Fi channels readout with Si-PM arrays
6000 scint. tails
readout with Si-PMs
rate ~ several MHz / Sci-Fi channels
time resolution ~ few 100 ps
readout with wave-form digitizers
real time analysis
pileup separation
background rejection
huge data rate !

4. How To Measure Best Timing
Beam measurements
@ SLAC and FNAL
simulation of MCP with realistic noise
and best discriminators
J.-F. Genat et al., arXiv: (2008)
D. Breton et al., NIM A629, 123 (2011)
17 ps (s) can be achieved with waveform digitizing and 40 photoelectrons

5. Switched Capacitor Arrayns
Inverter “Domino” ring chain IN
Waveform
stored
Out
FADC
33 MHz
Clock
Shift Register
“Time stretcher” GHz  MHz

6. DRS4 @ PSI http://drs.web.psi.ch
S. Ritt
DRS4 Evaluation Board 4 channels 1-5 GSPS 12 bit
USB power

7. New DRS4 Boards Under Development @PSI
S. Ritt
Integrate DRS and trigger on same board
Digitize all inputs continuously with 65 MHz / 12 bit
Upon trigger
read DRS through same ADC
Add local discriminators for fast trigger
Go away from VME
Higher density
Cheaper
Faster
Still crate based
“Added value” to DAQ boards
Switchable gain amplifiers
MPPC biasing integrated
DRS4
trigger
FPGA
MUX
DRS
AD bit
65 MHz
analog front end
global trigger bus
LVDS
Inputs
“Dead” space

8. Block Schematics (PSI)
S. Ritt
16 Channels on one Euro-card
triggering
MPPC biasing
Gain 0.1 … 100 selectable
Either standalone (Gbit Ethernet) or in crate

9. Next Generation SCA (DRS5)
Short sampling depth
Deep sampling depth
Low parasitic input capacitance  high bandwidth
Large area  low resistance bus
low resistance analog switches  high bandwidth
Digitize long waveforms
Accommodate long trigger delay
Faster sampling speed for a given trigger latency
only short segments of waveform need fast speed readout

10. The DRS5 Digitizer S. Ritt 100 ps sample time. 3.1 ns hold time
2-5 times better timing resolution
data driven readout
dead-time-less waveform digitizing
2 MHz sustained event rate
planned for 2013

11. Digital Constant Fraction Discriminator
Delayed
signal
¼ max ampli
Inverted
signal t
used at BNL
~500 MHz digitizer
(continuous, no dead time)
0.5 ns resolution in real time !
(with linear interpolation)
and 10 MHz rate
Sum
Clock
12 bit
Latch
Latch
Latch
Latch +
Latch
Latch S +
<0
&
MULT 0

12. UNIGE Involvement / Plans (DRS ® ToF)
Mu3e ® 2014
mainly firmware development (algorithms)
new DRS4 boards developed by PSI
selectable gain, on board triggering, MPPC bias, etc.
AIDA (future n experiments) ® 2014
10 k channel (prototype detector) readout with DRS4 or DRS5
develop our own DRS boards (format) ® reduce cost < 100 CHF / ch. ?
input stage (differential)
calibration procedures (SCA requires frequent recalibration !)
clock distribution
commercial ADC (8 ch. / 12 bit / 66 MHz)
FPGA
on board memory
develop full readout chain
data concentrators
links to DAQ computers
NA61 ® 2014
synergy between NA61 and our projects ?
NA61: develop data concentrators and DDL links

13. Trigger during 2011 Heavy Ion Run
Heavy Ion Trigger implemented on the “fly”
(PSD detector, Z counters, etc.)
straightforward: “linear” and “simple” logic (also for the future !)
worked reliably during the whole HI data taking period
(incl. changes for different PSD positions)
some solutions not very “professional” because of lack of
appropriate hardware
while the existing scheme is working correctly,
can make it more robust for the future ® new hardware
Same approach in 2012

14. Trigger Improvements spares    DAQ scalers
- not reliable at all (scaler readout dead time / DAQ dead time)
- replaced with trigger monitoring scalers
(role to monitor online the trigger functioning, not to use in the offline analysis)
New Firmware
- existing firmware works reliably (one bug ® feature)
- “vetoing logic” can be improved
- additional monitoring triggers
S1 discriminator with veto
- discrepancy between the # of dead time gated triggers vs. # DAQ acc. triggers
- source: busy logic (fixed) and pre-trigger veto
(new veto scheme ® new S1 discri)
- reduce substantially the pre-trigger rate
PSD fast summation electronics
- remove jitter in the PSD signal
- improve the PSD timing (~1 ns)
- PSD thresholds computer controlled
spares   
COMPASS HCAL trigger

15. Forward Tracking
In NA49 used VETO chambers to measure forward protons and neutrons.
Even with simple tracking ® interesting results
In NA61 large amount of data being
collected with p (or p) beams:
it is a pity to neglecting the forward region
and neutrons (PSD !)
potentially interesting physics
For xF > 0.7, most particles are protons
(or neutrons) , no need for PID
A set of 60 ´ 60 cm2 MWPCs would suffice to cover this region !
HCAL
diffractive peak