1. EEL 3705 / 3705L Digital Logic Design
Fall 2006 Instructor: Dr. Michael Frank Module #2: Lab Introduction & HW/SW Tools
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M. Frank, EEL3705 Digital Logic, Fall 2006

2. M. Frank, EEL3705 Digital Logic, Fall 2006
Lecture Outline
Administrative matters:
Turn in prereq form, if not already
1st-week Lab Administrivia / Handouts:
Attendance sheet, prereq form, syllabus, guidelines
Lab Introduction
List of Lab Assignments
Lab Notebook Guidelines
Overview of the HW/SW tools to be used in lab & for your design projects:
Altera UP2 development board
Altera FLEX 10K and MAX 7000 PLDs
Quartus II logic development software tool
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M. Frank, EEL3705 Digital Logic, Fall 2006

3. Planned Lab Assignments for Fall ‘06
Introduction to Basic Gates (AND, OR, XOR) With Quartus Software
ADDER, SUBTRACTOR, OR and AND Functions With a Selector Module
Arm/Disarm a Weapon of Mass Destruction
Top Secret Code Display
Electronic Device Test
Comparators
Arithmetic Functions and Selectors
Random Counter
Interface design to the TLC0831 analog-to-digital converter
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M. Frank, EEL3705 Digital Logic, Fall 2006

4. Guidelines for Use of Lab Notebooks
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M. Frank, EEL3705 Digital Logic, Fall 2006

5. Altera UP2 development board
Read the User Guide for details
From University Program UP2 Education Kit
Includes two PLDs (prog. logic devs.):
EPF10K70 – Member of the FLEX 10K family of PLDs
EPM7128S – Member of the MAX 7000 family of PLDs
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M. Frank, EEL3705 Digital Logic, Fall 2006

6. UP2 Board with Cable Connections
 To 9V Power Supply
JTAG Program- ming Cable
VGA Cable (to monitor)
Mouse cable
 To PC Parallel Port
FLEX PLD
MAX PLD
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M. Frank, EEL3705 Digital Logic, Fall 2006

7. M. Frank, EEL3705 Digital Logic, Fall 2006
UP2 Board Close-Up
PWR in
JTAG in
PS2 in
VGA out
FLEX Expansion Holes
7-Segment Display
Crystal
Jumpers
FLEX 10K
7-Segment Display
MAX Expansion Holes
LED banks
MAX 7000
FLEX DIP switch
FLEX Pushbuttons
MAX Pushbuttons
MAX DIP switches
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M. Frank, EEL3705 Digital Logic, Fall 2006

8. M. Frank, EEL3705 Digital Logic, Fall 2006
Altera MAX 7000S series PLD
Full part number: EPM7128SLC84-7
84-pin PLCC package
Plastic J-Lead Chip Carrier
2,500 usable gates
128 Macrocells
8 LABs
Logic Array Blocks
Chip socket
Pins
Female pin headers
PLCC Chip Package
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M. Frank, EEL3705 Digital Logic, Fall 2006

9. M. Frank, EEL3705 Digital Logic, Fall 2006
Altera FLEX 10K70 PLD
Full part number of our chip: EPF10K70RC240-4
240-pin RQFP package
poweR Quad Flat Pack
3,744 LEs (Logic Elements)
ea. w. 4-input LUT (Look-Up Table), flip-flop, routing
468 LABs (Logic Array Blocks)
group the LEs together into 8-bit arrays
9 EABs (Embedded Array Blocks)
2,048 bits each for programmable “megafunctions”
70,000 typical gates
118,000 max
Pins
RQFP Chip Package
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M. Frank, EEL3705 Digital Logic, Fall 2006

10. Quartus II Logic Development Tool
Supports the devices on our development board
You can download a free version from Altera
University-licensed version is installed on most college machines
Extensive free documentation, tutorials, etc. can be downloaded from Altera’s website
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M. Frank, EEL3705 Digital Logic, Fall 2006

11. Quartus II Built-In Tutorial
Try going through this to gain some initial familiarity with Quartus’ feature set and development flow
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M. Frank, EEL3705 Digital Logic, Fall 2006

12. Lab 1 Pre-Lab Materal: Logic Review / Preview
Basic logic gates: NOT, OR, AND, XOR
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M. Frank, EEL3705 Digital Logic, Fall 2006

13. Why Bits (Binary Digits)?
As we’ll learn, computers represent all information using bits.
A bit means a binary (i.e., base 2) digit, 0 or 1.
This is done for several reasons:
Two states (digit values) is all that is really needed.
Any desired information can be represented using sequences of bits.
Encoding information using 2-state systems offers the best noise immunity for a given energy/information ratio.
Computers based on bits tend to be the most energy-efficient.
A bit conveniently can represent the truth value of any given proposition in Boolean logic.
That is, “true” (1) or “false” (0).
Bits can be simply and easily manipulated by simple hardware elements called “logic gates.”
These implementing the basic operators of Boolean logic.
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M. Frank, EEL3705 Digital Logic, Fall 2006

14. M. Frank, EEL3705 Digital Logic, Fall 2006
Boolean Logic: Review
For reasoning about whether propositions (statements) are true (T) or false (F).
The truth value of the proposition.
The important functional operators of Boolean logic include:
NOT(x) = {T iff x=F (otherwise F)}
AND(x,y) = {T iff both x=T and y=T}
OR(x,y) = {T iff either x=T or y=T, or both}
XOR(x,y) = {T iff either x=T or y=T, but not both}
George Boole
iff = “if and only if”
 “exclusive OR”
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M. Frank, EEL3705 Digital Logic, Fall 2006

15. Boolean Logic Notations
You should be aware that any given expression of Boolean logic could be written in several styles:
Writing operators as functions:
XOR(OR(AND(a,b),NOT(c)),d)
Using operator names “infix” (between their operands):
((a AND b) OR (NOT c)) XOR d
Using mathematical logic operator symbols:
[(a  b)  ¬c]  d
Using C programming language operators:
((a & b) | ~c) ^ d
Using Boolean algebra notation:
Preferred in this course
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M. Frank, EEL3705 Digital Logic, Fall 2006

16. M. Frank, EEL3705 Digital Logic, Fall 2006
Logic Gate Icons
Inverter
Logical NOT, Boolean complement
AND gate
Boolean product
OR gate
Boolean sum
XOR gate
exclusive-OR, sum mod 2 x x
x·y y x
x+y y x
x⊕y y
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M. Frank, EEL3705 Digital Logic, Fall 2006

17. M. Frank, EEL3705 Digital Logic, Fall 2006
Multi-input AND, OR, XOR
Can extend these gates to arbitrarily many inputs.
Two commonly seen drawing styles:
Note that the second style keeps the gate icon relatively small. x1
x1x2x3 x2 x3
x1 ⋮ x5
x1…x5
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M. Frank, EEL3705 Digital Logic, Fall 2006

18. M. Frank, EEL3705 Digital Logic, Fall 2006
NAND, NOR, XNOR
Just like the earlier icons, but with a small circle on the gate’s output.
Denotes that the output is complemented.
Circles could also be placed on inputs.
Means, input is complemented before being used. x y x y x y
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M. Frank, EEL3705 Digital Logic, Fall 2006

19. CMOS NAND gate implementation
A NAND gate is particularly easy to implement in CMOS:
Simple 4-transistor circuit 
A NOR gate is equally simple,
but slower,
due to series pFETs
If we wanted to, we could build any computer using nothing but NAND gates and wires!
Vdd x y xy
Vss = GND
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M. Frank, EEL3705 Digital Logic, Fall 2006

20. Lab 1 Goal: Confirm Function of AND/OR/XOR Gates in Quartus
At the conclusion of lab 1, you should have obtained results that confirm the expected outputs of the AND, OR, and XOR gates for all four possible combinations of two input bits.
Below, A and B are 4-bit signals that (at the specific time point sampled below) give the two input bits in each of the four different possible cases, while W, Y, and Z represent the corresponding outputs of the OR, AND, and XOR functions respectively.
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M. Frank, EEL3705 Digital Logic, Fall 2006