6. TITLE ASSEMBLY LANGUAGE DEFINITION FILE FOR UP1 COMPUTER DESIGN
WORD 16
WIDTH 72
LINES 50
;******************************************************************
; INSTRUCTION OPCODE LABELS - MUST BE 8-BITS, 2 Hex DIGITS
LADD: EQU H#00
LSTORE: EQU H#01
LLOAD: EQU H#02
LJUMP: EQU H#03
LJNEG: EQU H#04
LSUB: EQU H#05
LXOR: EQU H#06
LOR: EQU H#07
LAND: EQU H#08
LJPOS: EQU H#09
LZERO: EQU H#0A
LADDI: EQU H#0B
LSHL: EQU H#0C
LSHR: EQU H#0D
LIN: EQU H#0E
LOUT: EQU H#0F
LWAIT: EQU H#10

7. ;******************************************************************
; DATA PSEUDO OPS
;DB: DEF 8VH# ;8-BIT DATA DIRECTIVE
DW: DEF 16VH#0000 ;16-BIT DATA DIRECTIVE
;ASSEMBLY LANGUAGE INSTRUCTIONS
ADD: DEF LADD,8VH#00
STORE: DEF LSTORE,8VH#00
LOAD: DEF LLOAD,8VH#00
JUMP: DEF LJUMP,8VH#00
JNEG: DEF LJNEG,8VH#00
SUBT: DEF LSUB,8VH#00
XOR: DEF LXOR,8VH#00
OR: DEF LOR,8VH#00
AND: DEF LAND,8VH#00
JPOS: DEF LJPOS,8VH#00
ZERO: DEF LZERO,8VH#00
ADDI: DEF LADDI,8VH#00
SHL: DEF LSHL,H#0,4VH#0
SHR: DEF LSHR,H#0,4VH#0
IN: DEF LIN,8VH#00
OUT: DEF LOUT,8VH#00
WAIT: DEF LWAIT,8VH#00
END

8. TITLE EXAMPLE UP1 COMPUTER ASSEMBLY LANGUAGE TEST PROGRAM
LIST F,W
LINES 50
;*********************************
; MACROS
ECHO: MACRO PORT
IN PORT
OUT PORT
ENDM
; CONSTANTS
CON1: EQU 2
DISPLAY: EQU H#00
SWITCH: EQU H#01
; PROGRAM AREA
ORG H#00
START: LOAD LABEL1%:
ADDI 1%:
SHL 1
SHR CON1%:
AND H#0F
OR H#80
SUBT LABEL2%:
JPOS ENDP%:
XOR LABEL3%:
ADD (TABLE1 + 3)%:
JNEG ENDP%:
IN SWITCH
OUT DISPLAY

9. ; MACRO TEST
ECHO H#10
WAIT B#
ENDP: STORE LABEL1%:
LOOP: JUMP LOOP%:
JUMP START<%:
JUMP $%:
;********************************
; DATA FOR TEST PROGRAM
ORG H#80
LABEL1: DW H#0ACE
LABEL2: DW H#0000
LABEL3: DW H#FFFF ;UNSIGNED LARGEST NUMBER
LABEL4: DW H#7FFF ;TWO'S COMPLEMENT LARGEST NUMBER
TABLE1: DW H#0000
DW H#0011
DW H#0022
DW H#0033
DW H#0044
DW H#0055
DW H#0066
DW H#0077
DW H#0088
END

10. Addr Line EXAMPLE UP1 COMPUTER ASSEMBLY LANGUAGE TEST PROGRAM
1 TITLE EXAMPLE UP1 COMPUTER ASSEMBLY LANGUAGE TEST PROGRAM
2 LIST F,W
3 LINES 50
4 ;*********************************
5 ; MACROS
6 ;*********************************
7 ECHO: MACRO PORT
IN PORT
OUT PORT
ENDM
11 ;*********************************
12 ; CONSTANTS
13 ;*********************************
14 CON1: EQU 2
15 DISPLAY: EQU H#00
16 SWITCH: EQU H#01
17 ;*********************************
18 ; PROGRAM AREA
19 ;*********************************

11. ORG H#00
START: LOAD LABEL1%:
B ADDI 1%:
C SHL 1%:
D SHR CON1%:
F AND H#0F
OR H#80
SUBT LABEL2%:
JPOS ENDP%:
XOR LABEL3%:
ADD (TABLE1 + 3)%:
0000A JNEG ENDP%:
0000B 0E IN SWITCH
0000C 0F OUT DISPLAY
34 ; MACRO TEST
ECHO H#10
0000D 0E IN H#10
0000E 0F OUT H#10
ENDM
0000F 10C WAIT B#
ENDP: STORE LABEL1%:
LOOP: JUMP LOOP%:
JUMP START%:
JUMP $%:

12. 43 ;******************************** 00080 44 ORG H#80
41 ;********************************
42 ; DATA FOR TEST PROGRAM
43 ;********************************
ORG H#80
ACE LABEL1: DW H#0ACE
LABEL2: DW H#0000
00082 FFFF LABEL3: DW H#FFFF ;UNSIGNED LARGEST NUMBER
FFF LABEL4: DW H#7FFF ;TWO'S COMPLEMENT LARGEST NUMBER
TABLE1: DW H#0000
DW H#0011
DW H#0022
DW H#0033
DW H#0044
DW H#0055
0008A DW H#0066
0008B DW H#0077
0008C DW H#0088
58 END

15. S t a e D i g r m R s A B C O u p 1 X

16. V H D L S t a t e M a c h i n e M o d e l V e r i l o g S t a t e M ay s a _ m c h p o r ( l k , : d g ; u 1 2 ) A f S T E Y P s ; e n d a m o u l t _ c h ( k , r i p 1 2 ) g [ : ] A = E i s ( t a e _ A , B C ) ; g n l : S T Y P b p r o c k f = ' 1 h
< V N d t e _ B = 1 , s a C 2 ; l w y @ ( p o d g c k r ) b i n f A : u t a e i s w h n _ A =
> f p u 1 '
< B ; l C d s t a e = _ B ; l C : i f ( n p u 2 ) w h e n s t a _ B =
>
< C ; i f p u 2 ' 1 A d c e _ A ; n d c a s l w y @ ( t ) b g i : o u p 1 = B C f a s e ; n d i f p r o c w t h l u 1
< = ' _ A , B C e n d c a s e e n d e n d m o d u l e

17. B k D i a g m A L U _ c o n t r l ( 2 . 1 ) 6 p u S h f e R + , - N Op u S h f e R + , - N O s C

18. V H D M e n t i y A L U s p o r ( _ c l : d g v 2 w ) ; u , B 1 5 C k) ; u , B 1 5 C k R a h T f b
" =
>
< + - ' 4
& m [ ] @ 3 | V H D M 1 6

19. //Simple Computer Design from Chapter 8 in Verilog
module SCOMP (clock,reset,program_counter,register_A,
memory_data_register_out, instruction_register);
input clock,reset;
output [7:0] program_counter;
output [15:0] register_A, memory_data_register_out, instruction_register;
reg [15:0] register_A, instruction_register;
reg [7:0] program_counter;
reg [3:0] state;
reg [7:0] memory_address_register;
reg memory_write;
// State Encodings
parameter reset_pc = 0,
fetch = 1,
decode = 2,
execute_add = 3,
execute_store = 4,
execute_store2 = 5,
execute_store3 = 6,
execute_load = 7,
execute_jump = 8;
wire [15:0] memory_data_register;
wire [15:0] memory_data_register_out = memory_data_register;
wire [15:0] memory_address_register_out = memory_address_register;
wire memory_write_out = memory_write;

20. // Use LPM function for computer's memory (256 16-bit words)
LPM_RAM_DQ LPM_RAM_DQ_component (
.address (memory_address_register_out),
.inclock (clock),
.data (register_A),
.we (memory_write_out),
.q (memory_data_register));
defparam
LPM_RAM_DQ_component.LPM_WIDTH = 16,
LPM_RAM_DQ_component.LPM_WIDTHAD = 8,
LPM_RAM_DQ_component.LPM_INDATA = "REGISTERED",
LPM_RAM_DQ_component.LPM_ADDRESS_CONTROL = "UNREGISTERED",
LPM_RAM_DQ_component.LPM_OUTDATA = "UNREGISTERED",
LPM_RAM_DQ_component.USE_EAB = "ON",
// Reads in mif file for initial program and data values
LPM_RAM_DQ_component.LPM_FILE = "program.mif";

21. // reset the computer, need to clear some registers reset_pc :
clock or posedge reset)
begin
if (reset)
state = reset_pc;
else
case (state)
// reset the computer, need to clear some registers
reset_pc :
program_counter = 8'b ;
memory_address_register = 8'b ;
register_A = 16'b ;
memory_write = 0;
state = fetch;
end
// Fetch instruction from memory and add 1 to program counter
fetch :
instruction_register = memory_data_register;
program_counter = program_counter + 1;
state = decode;

22. // Decode instruction and send out address of any data operands
begin
memory_address_register = instruction_register[7:0];
case (instruction_register[15:8])
8'b :
state = execute_add;
8'b :
state = execute_store;
8'b :
state = execute_load;
8'b :
state = execute_jump;
default:
state = fetch;
endcase
end
// Execute the ADD instruction
execute_add :
register_A = register_A + memory_data_register;
memory_address_register = program_counter;

23. // Execute the STORE instruction,needs 3 clock cycles for memory write)
execute_store :
begin
// write register_A to memory
memory_write = 1;
state = execute_store2;
end
// This state ensures that the memory address is valid until
// after memory_write goes low
execute_store2 :
memory_write = 0;
state = execute_store3;
execute_store3 :
memory_address_register = program_counter;
state = fetch;

24. // Execute the LOAD instruction
execute_load :
begin
register_A = memory_data_register;
memory_address_register = program_counter;
state = fetch;
end
// Execute the JUMP instruction
execute_jump :
memory_address_register = instruction_register[7:0];
program_counter = instruction_register[7:0];
// Default case – an undefined opcode
default :
memory_write = 0;
endcase
endmodule