1. The DHCAL DIF Board For the M2 Prototype
Julie Prast, LAPP, Annecy

2. Architecture of the DIF board
Power Supplies+/- 6V
+/-5V 3.3V 2.5V …..
LDO
Monitoring
Mezzanine
JTAG
USB
FPGA
ASIC Config
ASIC read
DAQ interface
Slow control
SLAB
LDA (HDMI)
EP3C16F484
DAQ0 (SCSI)
ADC
HARDROCs analog output
DIF
10 January 2008
The DHCAL DIF Board for the m2 Prototype

3. The DHCAL DIF Board for the m2 Prototype
The Analog Part
Addr
FPGA
USB
En_otaq<1..32>
EP3C16F484
DEMUX
SLAB
ADC
AD9220
DAQ0
HARDROCs analog output
An ADC has been added to read the analog output from the FPGA (ie without the analog DAQ).
ADC 12 bits, 10MSPS, already tested by LAL team : AD9220.
One ASIC among 32 max, is selected from the FPGA using the en_otaq signal. To decrease the nb of pins on the FPGA a DEMUX is used.
10 January 2008
The DHCAL DIF Board for the m2 Prototype

4. The DHCAL DIF Board for the m2 Prototype
Separated from the slab for more flexibility.
Can handle slab what ever the nb of HardRoc on it.
Compatible with the DIF Task Force.
Interfaces with :
The final DAQ (LDA, …)
The analog DAQ
Neighboring DIFs.
PC through USB for standalone tests and debugs.
Handle HardROC power cycling.
Compatible with the ASIC of IPN Lyon.
High voltage is not foreseen.
10 January 2008
The DHCAL DIF Board for the m2 Prototype

5. Interface with the SLAB
Use of a small intermediate board, which is specific to the FE ASIC and ASU.
The DIF can be used :
Whatever the FE ASIC.
Whatever the slab (RPC, uM)
Whatever the slab to slab connection.
1rst ASU is the same as the others.
DIF
Intermediate
board
Samtec FSH/ SFMH ?
Connector to be chosen. No special constraint.
Connection with the slab is the same as the one between 2 ASUs.
0 Ω resistor, …
10 January 2008
The DHCAL DIF Board for the m2 Prototype

6. The DHCAL DIF Board for the m2 Prototype
Still a lot to do …
Electrical schemes to be finalized :
Finalize FPGA pin out.
Finalize LDA to DIF interface (cable length and type, electrical terminations, …)
Finalize connectors choice.
Finalize analog part : EL2140 ? Analog buffer ?
And all the CAD and the VHDL code …
Additional human resources for coming months :
Sebastien Cap from LAPP for the CAD.
Guillaume Vouters (engineer student) between March and August for VHDL, tests, ….
10 January 2008
The DHCAL DIF Board for the m2 Prototype

7. Status and Agenda Schemes are being done.
Will be circulated before the end of the month.
=> Inputs are very welcome.
First prototype is awaited for May.
Expect performing main tests before summer.
Chistophe Combaret (Lyon) is in charge of the test Software.
DIFs should be available for the m2 test at the beginning of the fall (end of the summer for Imad).
10 January 2008
The DHCAL DIF Board for the m2 Prototype

8. The DHCAL DIF Board for the m2 Prototype
VHDL Librairies
One of the aim of the DIF task force is to create a repository for the VHDL blocks that can be common for the different subdetector groups :
I proposed in a message sent on November 21st to collect and order them.
Christophe Combaret will manage the storage server at IPNL.
Bart sent a kind of DIF architecture.
Francois Wicek sent the slow control block for skiroc.
Now we need more contributions to get richer the librairie.
10 January 2008
The DHCAL DIF Board for the m2 Prototype