1. D.4 Finite State Diagram for the Multi-cycle processor
Add State 10; State 11
State transitions for addi:
S0 S1S10S11S0

2. The Multicycle Datapath with Control Signals
PCWriteCond
PCWrite
PCSource
IorD
ALUOp
MemRead
Control
ALUSrcB
MemWrite
ALUSrcA
MemtoReg
RegWrite
IRWrite
RegDst
PC[31-28]
Instr[31-26]
Shift
left 2 28
Instr[25-0] 2 1
Address
Memory PC
Read Addr 1 A IR
Read
Data 1
Register
File 1 1
zero
Read Addr 2
Read Data
(Instr. or Data)
ALUout
ALU
Write Addr
Write Data 1
Read
Data 2 B
MDR 1
Write Data 4 1 2
Instr[15-0]
Sign
Extend
Shift
left 2 3 32
ALU
control
Instr[5-0]

3. To implement addi, two extra states are added, state 10 and state 11
State 10: performing Rs + immediate ;
Control Signals at State 10: ALUSrcA=1; ALUSrcB=10; ALUop=10
State 11: write the ALU output to Rt
Control signals at State 11: MemtoReg=0; RegDst=0; RegWrite=1
Need
One product term to implement from State1 to State10 when Opcode is addi
Two product terms for S10 and S11

4. Add Three
Product
terms here
S10;
S11;
S1 and with
Opcode of addi
001000
Product terms in PLA
s0 s1 s2 s3 s4 s5 s6s7 s8 s9