1. Progress Report
Chester Liu
2013/11/29

2. OpenDVC Website

3. H264 Encoder C Model
Need to generate test patterns for Verilog simulation
C model software package is based on Visual Studio
Method 1: port C code to Linux failed
Method 2: use winegcc to compile failed
Method 3: use wine to execute binary compiled by Visual Studio pass
Run C model to generate test patterns and run Verilog simulation pass
Change PeriodOfIntraFrames from 0 to 1 in H264Enc.cfg

4. H264 Encoder Interface Control interface (slave)
Read/write memory mapped register (MMR)
ahb_o_data output MMR value when ahb_i_en_slave = 1
Indicate encoding done
System bus interface (master)
Read raw data & write encoded data
No data handshake
Raw data have to be arranged by MB order, not frame order
Local bus interface (master)
Read/write reference frames
Write reconstructed frames

5. H264 Encoder Registers Total 27 registers
11 registers are used when encoding the first MB in an intra slice
0x08 INTRA_CTRL
Current MB QP, is top / bottom / left / right MB, QUANT
0x09 INTRA_CURR_FRAME_Y_ADDR
0x0A INTRA_CURR_FRAME_U_ADDR
0x0B INTRA_CURR_FRAME_V_ADDR
0x14 EC_CTRL
Slice QP, slice header information
0x16 EC_SLICE_HEADER_ADDR
0x17 EC_SLICE_BITSTREAM_ADDR
0x18 DB_REC_FRAME_Y_ADDR
0x19 DB_REC_FRAME_U_ADDR
0x1A DB_REC_FRAME_V_ADDR
0x00 ENC_CTRL
Start, is intra, image width
2 registers are used when encoding the other MBs in an intra slice
0x08 and 0x00

6. H264 Encoder Headers
Encoder won’t generate SPS/PPS (sequence/picture parameter set)
Encoder pack given slice header with bit stream
Dr. Huang assumed these are handled by a CPU

7. H264 Encoder Slice Header (I)
How encoder get the slice header
CPU generate the slice header and write it to system memory
CPU write MMR 0x14
BYTE_CNT byte count integer (ex: 71 bits, BYTE_CNT = 8)
BITSTOGO 8 – remaining bit count (ex: 71 bits, BITSTOGO = 8-7 = 1)
CONTENT remaining bit content
CPU write MMR 0x16

8. H264 Encoder Slice Header (II)
Example
Slice header
CPU write 0x to address 0xdeadbeee
CPU write 0x to address 0xdeadbeef
CPU write MMR 0x14
BYTE_CNT = 8
BITSTOGO = 1
CONTENT =
CPU write 0xdeadbeee to MMR 0x16

9. Plan First version Second version Resolution: QCIF (176 x 144)
So the entire system can fit in the FPGA on DE2-115
Only intra-encoded frames
Run JM to decode bit stream
Check if bit stream encoded by H264ENC can be decoded by JM pass
Expect to demo on 12/20
Second version
Add WZ encoder
Check if bit stream is decodable not sure
Expect to demo on 1/3

10. DVC System Architecture
Camera controller
Convert BT.656 YUV422 to YUV420
Store captured image in MB order
System SRAM*
80KB true dual port SRAM
W176 x H144 x 1.5B x 2 frames = 74.25KB
Local SRAM*
Bit stream SRAM*
1KB simple dual port SRAM
System controller
Control all other modules
Generate slice header for H264ENC
*FPGA on DE2-115 contains 486KB SRAM

11. Current Progress H264ENC System controller
Simulation with FPGA SRAM pass
Trial synthesis result
Logic elements: / (31%)
Memory bits: / (2%)
Maximum frequency: 34MHz
System controller
FSM for controlling H264ENC almost done

12. verdi –f filelist.f