1. High Performance Switches and Routers: Theory and Practice
Hot Interconnects 7
August 20, 1999
Stanford University
CTO and Founder
Abrizio Inc.
Nick McKeown
Assistant Professor of Electrical Engineering
and Computer Science

2. Tutorial Outline Introduction: What is a Packet Switch?
Packet Lookup and Classification: Where does a packet go next?
Switching Fabrics: How does the packet get there?
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3. Introduction What is a Packet Switch?
Basic Architectural Components
Some Example Packet Switches
The Evolution of IP Routers
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4. Basic Architectural Components
Congestion
Control
Admission
Control
Control
Reservation
Routing
Datapath:
per-packet
processing
Output
Scheduling
Switching
Policing
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5. Basic Architectural Components Datapath: per-packet processing3. 1.
Output
Scheduling 2.
Forwarding
Table
Interconnect
Forwarding
Decision
Forwarding
Table
Forwarding
Decision
Forwarding
Table
Forwarding
Decision
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6. Where high performance packet switches are used
Enterprise WAN access
& Enterprise Campus Switch
- Carrier Class Core Router
- ATM Switch
- Frame Relay Switch
Edge Router
The Internet Core
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7. Introduction What is a Packet Switch?
Basic Architectural Components
Some Example Packet Switches
The Evolution of IP Routers
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8. ATM Switch Lookup cell VCI/VPI in VC table.
Replace old VCI/VPI with new.
Forward cell to outgoing interface.
Transmit cell onto link.
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9. Ethernet Switch Lookup frame DA in forwarding table.
If known, forward to correct port.
If unknown, broadcast to all ports.
Learn SA of incoming frame.
Forward frame to outgoing interface.
Transmit frame onto link.
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10. IP Router Lookup packet DA in forwarding table.
If known, forward to correct port.
If unknown, drop packet.
Decrement TTL, update header Cksum.
Forward packet to outgoing interface.
Transmit packet onto link.
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11. Introduction What is a Packet Switch?
Basic Architectural Components
Some Example Packet Switches
The Evolution of IP Routers
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12. First-Generation IP Routers
Shared Backplane
CPU
Buffer
Memory
CPU
Memory
Line Interface
Line
Interface
DMA
MAC
Line
Interface
DMA
MAC
Line
Interface
DMA
MAC
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13. Second-Generation IP Routers
CPU
Buffer
Memory
Line
Card
DMA
MAC
Local
Buffer
Memory
Line
Card
DMA
MAC
Local
Buffer
Memory
Line
Card
DMA
MAC
Local
Buffer
Memory
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14. Third-Generation Switches/Routers
Switched Backplane
Line Interface
Line Interface
Line Interface
Line Interface
Line Interface
Line Interface
Line Interface
Line
Card
CPU
Card
Line
Card
Line Interface
CPU
Memory
Local
Buffer
Memory
Local
Buffer
Memory
MAC
MAC
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15. Fourth-Generation Switches/Routers Clustering and Multistage1 2 3 4 5 6 13 14 15 16 17 18 25 26 27 28 29 30 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 7 8 9 10 11 12 19 20 21 22 23 24 31 32 21
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16. Packet Switches References
J. Giacopelli, M. Littlewood, W.D. Sincoskie “Sunshine: A high performance self-routing broadband packet switch architecture”, ISS ‘90.
J. S. Turner “Design of a Broadcast packet switching network”, IEEE Trans Comm, June 1988, pp
C. Partridge et al. “A Fifty Gigabit per second IP Router”, IEEE Trans Networking, 1998.
N. McKeown, M. Izzard, A. Mekkittikul, W. Ellersick, M. Horowitz, “The Tiny Tera: A Packet Switch Core”, IEEE Micro Magazine, Jan-Feb 1997.
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17. Tutorial Outline Introduction: What is a Packet Switch?
Packet Lookup and Classification: Where does a packet go next?
Switching Fabrics: How does the packet get there?
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18. Basic Architectural Components Datapath: per-packet processing3. 1.
Output
Scheduling 2.
Forwarding
Table
Interconnect
Forwarding
Decision
Forwarding
Table
Forwarding
Decision
Forwarding
Table
Forwarding
Decision
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19. Forwarding Decisions ATM and MPLS switches
Direct Lookup
Bridges and Ethernet switches
Associative Lookup
Hashing
Trees and tries
IP Routers
CIDR
Patricia trees/tries
Other methods
Caching
Packet Classification
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20. ATM and MPLS Switches Direct Lookup
(Port, VCI)
VCI
Memory
Address
Data
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21. Forwarding Decisions ATM and MPLS switches
Direct Lookup
Bridges and Ethernet switches
Associative Lookup
Hashing
Trees and tries
IP Routers
CIDR
Patricia trees/tries
Other methods
Caching
Packet Classification
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22. Bridges and Ethernet Switches Associative Lookups
Advantages:
Simple
Disadvantages
Slow
High Power
Small
Expensive
Associative
Memory or CAM
log2N
Associated
Data
Hit?
Address {
Network
Address
Associated
Data
Search
Data 48
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23. Bridges and Ethernet Switches Hashing
log2N
Associated
Data
Hit?
Address {
Search
Data
Hashing
Function 16
Address
Memory
Data 48
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24. Lookups Using Hashing An example
Memory #1 #2 #3 #4
log2N
Associated
Data
Hit?
Address {
Search
Data
Hashing Function 16 #1 #2 48
CRC-16
M entries
N lists #1 #2 #3
Linked lists
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25. Lookups Using Hashing Performance of simple example
Most addresses in one list
Most addresses in their own list
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26. Lookups Using Hashing Advantages: Disadvantages Simple
Expected lookup time can be small
Disadvantages
Non-deterministic lookup time
Inefficient use of memory
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27. Trees and Tries Binary Search Tree Binary Search Trie 1 log2N1
111
010
log2N
N entries
<
>
<
>
<
>
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28. Trees and Tries Multiway tries
16-ary Search Trie
0000, ptr
1111, ptr
0000, 0
1111, ptr
0000, 0
1111, ptr
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29. Trees and Tries Multiway tries
Table produced from 215 randomly generated 48-bit addresses
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30. Forwarding Decisions ATM and MPLS switches
Direct Lookup
Bridges and Ethernet switches
Associative Lookup
Hashing
Trees and tries
IP Routers
CIDR
Patricia trees/tries
Other methods
Caching
Packet Classification
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31. IP Routers Class-based addresses
IP Address Space
Class A
Class B
Class C D
Class A
Class B
Class C
Port 4
Exact
Match
Routing Table:
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32. IP Routers CIDR Class-based: A B C D Classless: 128.9.16.14 232-1
232-1
Classless:
216
142.12/19
65/24
128.9/16
232-1
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33. IP Routers CIDR
/24
/24
/20
/20
Most specific route = “longest matching prefix”
128.9/16
232-1
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34. IP Routers Metrics for Lookups
128.9/16
/20
/20
/24
/24
142.12/19
65/24
Prefix
Port 3 5 2 7 10 1
Lookup time
Storage space
Update time
Preprocessing time
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35. IPv4 unicast destination address based lookup
IP Router Lookup
Dstn Addr
Next Hop
----
Destination
Forwarding Table
Next Hop Computation
Forwarding Engine
Incoming Packet
HEADER
IPv4 unicast destination address based lookup
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36. Need more than IPv4 unicast lookups
Multicast
PIM­SM
Longest Prefix Matching on the source and group address
Try (S,G) followed by (*,G) followed by (*,*,RP)
Check Incoming Interface
DVMRP:
Incoming Interface Check followed by (S,G) lookup
IPv6
128­bit destination address field
Exact address architecture not yet known
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37. Lookup Performance Required
Gigabit Ethernet (84B packets): 1.49 Mpps
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38. Size of the Routing Table
About
10k new
prefixes
per year
Exponential
growth before
CIDR
Source:
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39. Method #1: Ternary CAMs Associative Memory Value Mask 10.0.0.0 R1 R2
Next Hop R3 R4 R4
Priority Encoder
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40. Method #2: Binary Tries 1 Example Prefixes a) 00001 b) 00010 c) 000111
Example Prefixes a) b) c)
d) 001
e) 0101 d f g
f) 011
g) 100 h i
h) 1010 e
i) 1100 a b c j) j
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41. Reduced number of memory accesses But greater wasted space...
Four-way tries
Reduced number of memory accesses
But greater wasted space...
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42. Method #3: Patricia Tree
Example Prefixes 1 a) b) c)
d) 001
Skip=5
e) 0101
f) 011 f g d j
g) 100
h) 1010 h e i
i) 1100 a b c j)
Disadvantages
Advantages
Many memory accesses
General solution
May need backtracking
Extensible to wider fields
Pointers take a lot of space
(Total storage for 40K entries is 2MB)
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43. Method #4: Level Compressed Triesj f g d c h b e i a .
Expected depth of a trie =
log *
n (=1+log *
(logn)) .
For bernoulli type distributions, expected depth = O(loglogn) .
Achieves approx 0.5Mpps on a Pentium with
a 40k routing table, occupying less than 0.8MB
Disadvantages
Advantages
No practical performance gain
May be useful forIPv6
Handling updates is complex
Nice theoretical idea
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44. Method #5: Compacting Forwarding Tables
Optimize the data structure to store 40, routing table entries in about kBytes.
Rely on the compacted data structure to be residing in the primary or secondary cache of a fast processor.
Achieves approx 2Mpps.
Disadvantages
Advantages
Only 60% actually cached
Good software solution for
Scalability to larger tables
low speeds and small routing
Handling updates is complex
tables.
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45. Method #6: A Hash-based Scheme
Example Prefixes
Example Prefixes
Store a hash table for each prefix length /8 /8
/16
/16
Length
Hash
/24
/24
/24
/24 8 10
/24
/24 12
Example Addrs 16
10.1, 10.2 24
10.1.1, ,
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46. A Hash-Based Scheme (contd.)
Binary search of the prefix lengths:
O(log
N )
hashes 2
Need to provide intermediate markers
But then we need precomputation per marker
Asymmetric binary search
Performance is about 2.2Mpps in the worst case for 33K table.
Disadvantages
Advantages
Need multiple hashes
Good software solution for
Scalability to larger tables
low speeds and small routing
Handling updates is complex
tables.
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47. Method #8: Routing Lookups in Hardware
Number
Prefix length
Most prefixes are 24-bits or shorter
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48. Routing Lookups in Hardware
Prefixes up to 24-bits
224 = 16M entries 1
Next Hop
Next Hop 24 14
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49. Routing Lookups in Hardware
Prefixes up to 24-bits 24
Pointer 8
Prefixes above
24-bits
Next Hop
offset
base 1
Next Hop 44
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50. Routing Lookups in Hardware (Contd.)
Prefixes up to n-bits
2n entries:
entries j
Prefixes
longer than
N+M bits i N
Next Hop
N + M
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51. Routing Updates Disadvantages Advantages Large memory required
Depth 3
Depth 2
Depth 1
Disadvantages
Large memory required
Depends on prefix length distribution
Advantages
20 Mpps with 50ns DRAM
Easy to implement in hardware
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52. IP Router Lookups References
A. Brodnik, S. Carlsson, M. Degermark, S. Pink. “Small Forwarding Tables for Fast Routing Lookups”, Sigcomm 1997, pp 3-14.
B. Lampson, V. Srinivasan, G. Varghese. “ IP lookups using multiway and multicolumn search”, Infocom 1998, pp , vol. 3.
M. Waldvogel, G. Varghese, J. Turner, B. Plattner. “Scalable high speed IP routing lookups”, Sigcomm 1997, pp
P. Gupta, S. Lin, N.McKeown. “Routing lookups in hardware at memory access speeds”, Infocom 1998, pp , vol. 3.
S. Nilsson, G. Karlsson. “Fast address lookup for Internet routers”, IFIP Intl Conf on Broadband Communications, Stuttgart, Germany, April 1-3, 1998.
V. Srinivasan, G.Varghese. “Fast IP lookups using controlled prefix expansion”, Sigmetrics, June 1998.
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53. Caching Addresses Slow Path Fast Path CPU Line Card Local Buffer
Memory
Fast Path
Line
Card
DMA
MAC
Local
Buffer
Memory
Line
Card
DMA
MAC
Local
Buffer
Memory
Line
Card
DMA
MAC
Local
Buffer
Memory
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54. Caching Addresses LAN: Average flow < 40 packets WAN:
Huge Number of flows
Cache = 10% of Full Table
Cache
Hit
Rate
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55. Forwarding Decisions ATM and MPLS switches
Direct Lookup
Bridges and Ethernet switches
Associative Lookup
Hashing
Trees and tries
IP Routers
CIDR
Patricia trees/tries
Other methods
Caching
Packet Classification
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56. Providing Value­Added Services Some examples
Differentiated services
Regard traffic from AS#33 as `platinum­grade’
Access Control Lists
Deny udp host eq snmp
Committed Access Rate
Rate limit WWW traffic from sub­interface#739 to 10Mbps
Policy­based Routing
Route all voice traffic through the ATM network
Peering Arrangements
Restrict the total amount of traffic of precedence 7 from
MAC address N to 20 Mbps between 10 am and 5pm
Accounting and Billing
Generate hourly reports of traffic from MAC address M
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57. Flow Classification Flow Index ---- Predicate Action Policy Database
Forwarding Engine
Incoming Packet
HEADER
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58. A Packet Classifier
Given a classifier, find the action associated with the highest priority rule (here, the lowest numbered rule) matching an incoming packet.
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59. Geometric Interpretation in 2D
Field #1
Field #2
Data R7 R6 R2 R1 P1 R4 P2 R5 R3
e.g. (144.24/16, 64/24)
e.g. ( , *)
Field #2
Field #1
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60. Proposed Schemes
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61. Proposed Schemes (Contd.)
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62. Proposed Schemes (Contd.)
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63. Packet Classification References
T.V. Lakshman. D. Stiliadis. “High speed policy based packet forwarding using efficient multi-dimensional range matching”, Sigcomm 1998, pp
V. Srinivasan, S. Suri, G. Varghese and M. Waldvogel. “Fast and scalable layer 4 switching”, Sigcomm 1998, pp
V. Srinivasan, G. Varghese, S. Suri. “Fast packet classification using tuple space search”, to be presented at Sigcomm 1999.
P. Gupta, N. McKeown, “Packet classification using intelligent hierarchical cuttings”, Hot Interconnects VII, 1999.
P. Gupta, N. McKeown, “Packet classification on multiple fields”, Sigcomm 1999.
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64. Tutorial Outline Introduction: What is a Packet Switch?
Packet Lookup and Classification: Where does a packet go next?
Switching Fabrics: How does the packet get there?
Copyright All Rights Reserved

65. Switching Fabrics Output and Input Queueing Output Queueing
Scheduling algorithms
Combining input and output queues
Multicast traffic
Other non-blocking fabrics
Multistage Switches
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66. Basic Architectural Components Datapath: per-packet processing3. 1.
Output
Scheduling 2.
Forwarding
Table
Interconnect
Forwarding
Decision
Forwarding
Table
Forwarding
Decision
Forwarding
Table
Forwarding
Decision
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67. Interconnects Two basic techniques
Input Queueing
Output Queueing
Usually a non-blocking
switch fabric (e.g. crossbar)
Usually a fast bus
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68. Interconnects Output Queueing
Individual Output Queues
Centralized Shared Memory
Memory b/w = 2N.R 1 2 N 1
Memory b/w = (N+1).R 2 N
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69. Output Queueing The “ideal”1 2 2 1 1
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70. Output Queueing How fast can we make centralized shared memory?
5ns SRAM
Shared
Memory
5ns per memory operation
Two memory operations per packet
Therefore, up to 160Gb/s
In practice, closer to 80Gb/s 1 2 N
200 byte bus
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71. Switching Fabrics Output and Input Queueing Output Queueing
Scheduling algorithms
Combining input and output queues
Multicast traffic
Other non-blocking fabrics
Multistage Switches
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72. Interconnects Input Queueing with Crossbar
Memory b/w = 2R
Scheduler
Data In
Data Out
configuration
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73. Input Queueing Head of Line Blocking
Delay
Load
58.6%
100%
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74. Head of Line Blocking
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75. Copyright 1999. All Rights Reserved

76. Copyright 1999. All Rights Reserved

77. Input Queueing Virtual output queues
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78. Input Queues Virtual Output Queues
Delay
Load
100%
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79. Input Queueing Can be quite complex! Memory b/w = 2R Scheduler
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80. Input Queueing Scheduling
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81. Input Queueing Scheduling1 7 1
Bipartite
Matching 1 2 3 4
(Weight = 18) 2 2 2 4 2 3 3 5 4 2 4
Request
Graph
Question: Maximum weight or maximum size?
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82. Input Queueing Scheduling
Maximum Size
Maximizes instantaneous throughput
Does it maximize long-term throughput?
Maximum Weight
Can clear most backlogged queues
But does it sacrifice long-term throughput?
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83. Input Queueing Scheduling1 2 1 2
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84. Input Queueing Longest Queue First or Oldest Cell First= { }
Queue Length
Weight
100%
Waiting Time 1 2 3 4 10 M a x i m u w e g h t
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85. Input Queueing Why is serving long/old queues better than serving maximum number of queues?
When traffic is uniformly distributed, servicing the maximum number of queues leads to 100% throughput.
When traffic is non-uniform, some queues become longer than others.
A good algorithm keeps the queue lengths matched, and services a large number of queues.
VOQ #
Avg Occupancy
Uniform traffic
VOQ #
Avg Occupancy
Non-uniform traffic
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86. Input Queueing Practical Algorithms
Maximal Size Algorithms
Wave Front Arbiter (WFA)
Parallel Iterative Matching (PIM)
iSLIP
Maximal Weight Algorithms
Fair Access Round Robin (FARR)
Longest Port First (LPF)
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87. Wave Front Arbiter Requests Match 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4
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88. Wave Front Arbiter
Requests
Match
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89. Wave Front Arbiter Implementation
Combinational Logic Blocks
1,1
1,2
1,3
1,4
2,1
2,2
2,3
2,4
3,1
3,2
3,3
3,4
4,1
4,2
4,3
4,4
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90. Wave Front Arbiter Wrapped WFA (WWFA)
N steps instead of
2N-1
Requests
Match
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91. Input Queueing Practical Algorithms
Maximal Size Algorithms
Wave Front Arbiter (WFA)
Parallel Iterative Matching (PIM)
iSLIP
Maximal Weight Algorithms
Fair Access Round Robin (FARR)
Longest Port First (LPF)
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92. Parallel Iterative Matching
Random Selection
Random Selection 1 2 3 4 1 2 3 4
Grant 1 2 3 4
Accept/Match 1 2 3 4 #1 #2
Requests 1 2 3 4 1 2 3 4
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93. Parallel Iterative Matching Maximal is not Maximum1 2 3 4 1 2 3 4
Accept/Match
Requests 1 2 3 4
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94. Parallel Iterative Matching Analytical Results
Number of iterations to converge:
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95. Parallel Iterative Matching
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96. Parallel Iterative Matching
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97. Parallel Iterative Matching
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98. Input Queueing Practical Algorithms
Maximal Size Algorithms
Wave Front Arbiter (WFA)
Parallel Iterative Matching (PIM)
iSLIP
Maximal Weight Algorithms
Fair Access Round Robin (FARR)
Longest Port First (LPF)
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99. iSLIP
Round-Robin Selection
Round-Robin Selection 1 2 3 4 1 2 3 4
Grant 1 2 3 4
Accept/Match 1 2 3 4 #1 #2
Requests 1 2 3 4 1 2 3 4
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100. iSLIP Properties Random under low load TDM under high load
Lowest priority to MRU
1 iteration: fair to outputs
Converges in at most N iterations. On average <= log2N
Implementation: N priority encoders
Up to 100% throughput for uniform traffic
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101. iSLIP
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102. iSLIP
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103. iSLIP Implementation Programmable Priority Encoder State Decision1 1
log2N
Decision
Grant
Accept 2 2 N
Grant
Accept
log2N N N N
Grant
Accept
log2N
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104. Input Queueing References References
M. Karol et al. “Input vs Output Queueing on a Space-Division Packet Switch”, IEEE Trans Comm., Dec 1987, pp
Y. Tamir, “Symmetric Crossbar arbiters for VLSI communication switches”, IEEE Trans Parallel and Dist Sys., Jan 1993, pp
T. Anderson et al. “High-Speed Switch Scheduling for Local Area Networks”, ACM Trans Comp Sys., Nov 1993, pp
N. McKeown, “The iSLIP scheduling algorithm for Input-Queued Switches”, IEEE Trans Networking, April 1999, pp
C. Lund et al. “Fair prioritized scheduling in an input-buffered switch”, Proc. of IFIP-IEEE Conf., April 1996, pp
A. Mekkitikul et al. “A Practical Scheduling Algorithm to Achieve 100% Throughput in Input-Queued Switches”, IEEE Infocom 98, April 1998.
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105. Switching Fabrics Output and Input Queueing Output Queueing
Scheduling algorithms
Combining input and output queues
Multicast traffic
Other non-blocking fabrics
Multistage Switches
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106. Input Queueing Speedup
Input queued switches can not easily control delay
But output queued switches can.
How can we emulate the behavior of an output queued switch?
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107. Output Queueing The “ideal”1 2 2 1 1
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108. Using Speedup 1 2
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109. Using Speedup = ? 1 1 N N N N Output Queued Switch
Combined Input-Output Queued Switch 1 N N N N
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110. Using Speedup Theorem:
For a switch with combined input and output queueing to exactly mimic an output queued switch, for all types of traffic, a speedup of 2-1/N is necessary and sufficient.
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111. Switching Fabrics Output and Input Queueing Output Queueing
Scheduling algorithms
Combining input and output queues
Multicast traffic
Other non-blocking fabrics
Multistage Switches
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112. Multicast Traffic
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113. Multicast Traffic
Virtual output (fanout) queues are not practical for multicast.
Fanout splitting leads to a large increase in throughput.
Scheduling is simpler than for unicast.
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114. Multicast Traffic Fanout splitting
No fanout splitting
Fanout splitting
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115. Multicast Traffic Scheduling1 1 1 2 3 4 1 1 2 2 2 2 3 3 3 3 4 4 4 4
Requests
Grant
Match
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116. Switching Fabrics Output and Input Queueing Output Queueing
Scheduling algorithms
Combining input and output queues
Multicast traffic
Other non-blocking fabrics
Multistage Switches
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117. Other Non-Blocking Fabrics Clos Network
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118. Other Non-Blocking Fabrics Clos Network
Expansion factor required = 2-1/N (but still blocking for multicast)
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119. Other Non-Blocking Fabrics Self-Routing Networks
000
000
001
001
010
010
011
011
100
100
101
101
110
110
111
111
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120. Other Non-Blocking Fabrics Self-Routing Networks
The Non-blocking Batcher Banyan Network
Batcher Sorter
Self-Routing Network 3 7 7 7 7 7 7
000 7 2 5 4 6 6
001 5 3 2 5 5 4 5
010 2 5 3 1 6 5 4
011 6 6 1 3 3 3
100 1 4 3 2 2
101 1 6 2 1 1
110 4 4 4 6 2 2
111
Fabric can be used as scheduler.
Batcher-Banyan network is blocking for multicast.
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121. Switching Fabrics Output and Input Queueing Output Queueing
Scheduling algorithms
Combining input and output queues
Multicast traffic
Other non-blocking fabrics
Multistage Switches
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122. Multistage switches Self-Routing
000
000
001
001
010
010
011
011
100
100
101
101
110
110
111
111
Stage-by-stage
flow-control
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123. Multistage switches Self-Routing
Multicast copy network
Buffered multistage switch
000
001
010
011
100
101
110
111
Stage-by-stage
flow-control
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124. Tutorial Outline Introduction: What is a Packet Switch?
Packet Lookup and Classification: Where does a packet go next?
Switching Fabrics: How does the packet get there?
Copyright All Rights Reserved

125. Basic Architectural Components
Congestion
Control
Admission
Control
Control
Reservation
Routing
Datapath:
per-packet
processing
Output
Scheduling
Switching
Policing
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126. Basic Architectural Components Datapath: per-packet processing3. 1.
Output
Scheduling 2.
Forwarding
Table
Interconnect
Forwarding
Decision
Forwarding
Table
Forwarding
Decision
Forwarding
Table
Forwarding
Decision
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