1. Lecture 14 Serial Communication Interface

2. Outline Serial Communications Interface Operation in UART Mode
Interrupt Sources
Registers
RSPI
I2C

3. Data Communications
The International Organization for Standardization (ISO) has organized network function in seven layers
Each layer provides a service to the layer above and communicates with the same layer’s software or hardware on other computers
Layers 5-7 are concerned with services for the applications
Layers 1-4 are concerned with the flow of data from end to end

4. Physical Layer (1) – Serial Communications
The basic premise of serial communications is that one or two wires are used to transmit digital data
An extra ground reference wire is also needed
Communication can be one way or two way, however most often two way, hence the need for two communication wires
Other wires are often used for other aspects of the communications such as; ground, “clear-to-send”, “data terminal ready”, etc.

5. Serial Communication Basics
Send one bit of the message at a time
Message field consists of:
Start bit (one bit)
Data (LSB first or MSB, and size – 7 or 8 bits)
Optional parity bit is used to make total number of 1s in data even or odd
Stop bit (one or two bits)
All devices on network or link must use same communications parameters, such as speed for example

6. Bit Rate vs. Baud Rate Bit Rate: Baud Rate:
How many data bits are transmitted per second
Baud Rate:
How many symbols are transmitted per second
A symbol may be represented by a voltage level, a sine wave’s frequency or phase, etc.
Extra symbols (channel changes) may be inserted for framing, error detection, acknowledgment, etc.
These reduce the bit rate
A single symbol might encode more than one bit
This increases the bit rate

7. UART Concepts
UART stands for Universal Asynchronous Receiver/Transmitter
Universal
Configurable to fit protocol requirements
Asynchronous
No clock line needed to de-serialize bits
Receiver/Transmitter
Signals can be both received and transmitted

8. General UART Concepts The UART subsystem consists of:
Two shift registers
Parallel to serial for transmit
Serial to parallel for receive
Programmable clock source
Clock must run at 8x or 16x desired bit rate
Error detection
Detect bad stop or parity bits
Detect receive buffer overwrite
Interrupt generators
Character received
Character transmitted, ready to send another

9. General UART Concepts (cont.)
A Serial Input Parallel Output (SIPO) shift register
[1]
A Parallel Input Serial Output (PISO) shift register
[1]

10. Serial Communications Interface
The RX210 Group has 13 independent serial communications interface (SCI) channels
The SCI is configured as SCIc module (SCI0 to SCI11) and SCId module (SCI12)
The SCIc (SCI0 to SCI11) can handle both asynchronous and clock synchronous serial communications
Asynchronous serial data communications can be carried out with standard asynchronous communications chips
Such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communications Interface Adapter (ACIA)
As an extended function in asynchronous communications mode, the SCI also supports smart card (IC card) interfaces conforming to ISO/IEC (standard for Identification Cards)
Single-master operation as an simple I2C bus interface and simple SPI interfaces are also supported
As well as the functions of the SCIc module, the SCId module (SCI12) supports an extended serial protocol
With a structure formed from Start Frames and Information Frames

11. Block Diagram

12. SCI in UART Mode
In order to communicate from the RX210 chip, you need to set up several registers, including:
Mode
Speed
Parity
Stop bits
Configuration
There are two primary “Data Registers”
SCIx.RDR (Receive Data Register)
SCIx.TDR (Transmit Data Register)

13. Operation in Asynchronous Mode (cont.)
Example of data format in asynchronous serial communications
With 8-bit data, parity, two stop bits
Any of 12 transfer formats can be selected according to the SMR setting

14. The SCI's transfer clock can be selected as
Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCKn pin
According to the setting of CM bit in SMR and CKE[1:0] bits in SCR
When an external clock is input to the SCKn pin
The clock frequency should be 16 times the bit rate (ABCS = 0)
8 times the bit rate (ABCS in SEMR = 1)
The base clock of TMR0 and TMR1 can be selected by the ACS0 bit in SEMR of SCIn (n = 5, 6, 12)
When the SCI is operated on an internal clock, the clock can be output from the SCKn pin
The frequency of the clock output is equal to the bit rate
The phase is such that the rising edge of the clock is in the middle of the transmit data

15. Setting up the Speed of the Serial Port
The speed of communications is a combination of
PCLK
Bits CKS in the SMR
The Bit Rate Register (BRR)
Formula:
B=bit rate, N=BRR setting, n=CKS setting
If you for example want to communicate at 38,400 bps, and your PCLK is 50 MHz, n should be set to 0 and N should be set to 40
SCI0.BRR.BYTE = 40;

16. Error Rate
Since you cannot get an exact value of xx.0 there is an error rate associated with calculating the bit rate
Formula:
For example, communication at 38,400 bps, with a PCLK of 50 MHz, n set to 0 and N set to 40 the percent error will be

17. Bit Rates and Percent Errors
[1]

18. The RTS function uses the function of output on RTSn# pin
CTS and RTS Functions
The CTS function is the use of input on the CTSn# pin in transmission control
Setting the SPMR.CTSE bit to 1 enables the CTS function
Placing the low level on the CTSn# pin causes transmission to start
Applying the low level to the CTSn# pin while transmission is in progress does not affect transmission of the current frame
The RTS function uses the function of output on RTSn# pin
A low level is output when reception becomes possible
Conditions for low-level output
The value of the RE bit in the SCR is 1
Reception is not in progress
There are no received data yet to be read
The ORER, FER, and PER flags in the SSR are all 0
Condition for high-level output
The conditions for low-level output have not been satisfied

19. SCI Asynchronous Mode Initialization
Before transmitting and receiving data
Start by writing the initial value “00h” to SCR
Whenever the operating mode or transfer format is changed, SCR must be initialized before the change is made
When the external clock is used in asynchronous mode, ensure that the clock signal is supplied even during initialization
Clearing the SCR.RE bit to 0 initializes neither the ORER, FER, and PER flags in SSR nor RDR
Switching the value of the SCR.TE bit from 1 to 0 or 0 to 1 while the SCR.TIE bit is 1 leads to the generation of a TXI interrupt request

20. SCI Asynchronous Mode Initialization (cont.)
Sample SCI initialization flowchart (asynchronous mode)

21. Asynchronous Mode Serial Data Transmission
In serial transmission, the SCI operates
The SCI transfers data from TDR to TSR when data is written to TDR in the TXI interrupt processing routine
The TXI interrupt at the beginning of transmission is generated
When the TE bit in SCR is set to 1 after the TIE bit in SCR is set to 1
Or when these two bits are set to 1 simultaneously
Transmission starts after the CTSE bit in SPMR is set to 0 (disabling the CTS function) or a low level on CTS# pin causes data transfer from TDR to TSR
If the TIE bit in SCR is 1 at this time, a TXI interrupt request is generated
Continuous transmission is obtainable by writing the next data for transmission to TDR in the TXI interrupt processing routine before transmission of the current data for transmission is completed
When TEI interrupt requests are in use, set the SCR.TIE bit to 0 (disabling TXI requests) and the SCR.TEIE bit to 1 (enabling TEI requests) after the last of the data to be transmitted are written to the TDR from the processing routine for TXI requests

22. Asynchronous Mode Serial Data Transmission (cont.)
Data is sent from the TXDn pin in the order
Start bit, transmit data, parity bit or multi-processor bit (may be omitted depending on the format), and stop bit
The SCI checks for updating of (writing to) TDR at the time of stop bit output
When TDR is updated, setting of the CTSE bit in SPMR to 0 (CTS function disabled) or a low level input on the CTSn# pin
Cause the next transfer of the next data
Transmission from TDR to TSR and sending of the stop bit
After that, serial transmission of the next frame starts
If TDR is not updated, the TEND flag in SSR is set to 1
The stop bit is sent, and then the mark state is entered in which 1 is output
If the TEIE flag in SCR is 1 at this time, a TEI interrupt request is generated
A sample flowchart for serial transmission in asynchronous mode

24. Asynchronous Mode Serial Data Transmission (cont.)
Example of operation for serial transmission in asynchronous mode
From the middle of transmission until transmission completion
With 8-bit data, parity, one stop bit

25. Asynchronous Mode Serial Data Reception
In serial data reception, the SCI operates
When the value of the RE bit in SCR becomes 1
The output signal on the RTSn# pin goes to the low level
When the SCI monitors the communications line
After detects a start bit, it performs internal synchronization, stores receive data in RSR, and checks the parity bit and stop bit
If an overrun error occurs, the ORER flag in SSR is set to 1
If RIE in SCR is 1 at this time, an ERI interrupt request is generated
Receive data is not transferred to RDR
If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR
If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR
When reception finishes successfully, receive data is transferred to RDR

26. Asynchronous Mode Serial Data Reception (cont.)
If RIE in SCR is 1 at this time, an RXI interrupt request is generated
Continuous reception is enabled by reading the receive data transferred to RDR in this RXI interrupt processing routine before reception of the next receive data is completed
Reading out the received data that have been transferred to RDR causes the RTSn# pin to output the low level
Example of SCI operation for serial reception in asynchronous mode
With 8-bit data, parity, one stop bit

27. Asynchronous Mode Serial Data Reception (cont.)
Example of SCI operation for serial reception in asynchronous mode
With 8-bit data, parity, one stop bit
When RTS function is used

28. Asynchronous Mode Serial Data Reception (cont.)
If a receive error is detected, an ERI interrupt request is generated but an RXI interrupt request is not generated
Data reception cannot be resumed while the receive error flag is 1
Clear the ORER, FER, and PER bits to 0 before resuming reception
Be sure to read the RDR during overrun error processing
The states of the SSR status flags and receive data handling when a receive error is detected

31. A different interrupt vector is assigned to an interrupt source
Interrupt Sources
A different interrupt vector is assigned to an interrupt source
Can be enabled or disabled with the enable bits in SCR
A TXI interrupt request is generated
When data for transmission are transferred from TDR to TSR
If the SCR.TIE bit is 1
A TXI interrupt request can also be generated by setting the SCR.TE bit to 1 after setting the SCR.TIE bit to 1
Or by using a single instruction to set the SCR.TE and SCR.TIE bit to 1 at the same time
A TXI interrupt request can activate the DTC or DMAC to handle data transfer

32. Interrupt Sources (cont.)
A TXI interrupt request is not generated
Setting the SCR.TE bit to 1 while the setting of the SCR.TIE bit is 0
Setting the SCR.TIE bit to 1 while the setting of the SCR.TE bit is 1
A TEI interrupt request is generated
When new data are not written by the time of transmission of the last bit of the current data for transmission
If the setting of the SCR.TEIE bit is 1
The SSR.TEND flag becomes 1
When the setting of the SCR.TE bit is 1, SSR.TEND retains 1
Until further data for transmission are written to the TDR
Writing data to the TDR leads to clearing of the SSR.TEND flag
After a certain time, discarding of the TEI interrupt request
An RXI interrupt request is generated
When received data are stored in the RDR
If the SCR.RIE bit is 1

33. Interrupt Sources (cont.)
An RXI interrupt request can activate the DTC or DMAC to handle data transfer
An ERI interrupt request is generated
Setting of any from among the ORER, FER, and PER flags in the SSR to 1 while the SCR.RIE bit is 1
An RXI interrupt request is not generated at this time
Clearing all three flags (ORER, FER, and PER) leads to discarding of the ERI interrupt request

34. Serial Communications and Interrupts
There are three separate threads of control in the program
Main program and subroutines it calls
Transmit ISR
Executes when UART is
ready to send another character
Receive ISR
Executes when UART receives
a character
Problem: Information needs to be
buffered between threads
Solution: circular queue with head
and tail pointers
One for Tx and one for Rx

35. Code Implementing Queues
Enqueue at tail
tail_ptr points to next free entry
Dequeue from head
head_ptr points to item to remove
#define the queue size makes it easy
to change in the future
One queue direction
Tx ISR unloads tx_q
Rx ISR loads rx_q
Other threads (e.g. main) load tx_q
and unload rx_q
Queue is empty if size == 0
Queue is full if size == Q_SIZE

36. Registers
Receive Shift Register (RSR)
Receive Data Register (RDR)
Transmit Shift Register (TSR)
Transmit Data Register (TDR)

37. Serial Mode Register (SMR)
This special function register is concerned with operational variations of the UART
The bits related to the SMR are:
CKS: transmission speed
MP: Multi processor (set to 0)
STOP: Stop bits
PM: Parity mode
PE: Parity Enable
CHR: Length of data
CM: Communications mode
The following slide contains the values each bit can be set to

38. Registers (cont.)
Serial Mode Register (SMR)

39. Serial Control Register (SCR)
This register is responsible for controlling the Serial Communications Interface; whether it is turned on or off, the choice of input clock to the shift register, and function of the SCK pin
The following two slide contains the values each bit can be set to as well as their description

40. Registers (cont.)
Serial Control Register (SCR)

41. Registers (cont.)
Serial Control Register (SCR)

42. Registers (cont.)
Serial Extended Mode Register (SEMR)

43. Registers (cont.)
SPI Mode Register (SPMR)

44. Registers (cont.)
I2C Mode Register 1 (SIMR1)

45. Registers (cont.)
Smart Card Mode Register (SCMR)

46. Serial Status Register (SSR)
The SSR is a read only register which indicates the status of the currently received byte over the corresponding SCI
TEND:
This flag is set at the end of transmission of a byte from the TDR or in case the serial transmission is disabled
PER:
Parity error flag
FER:
This flag indicates if there is a framing error
ORER:
Overrun error flag
MPB and MPBT bits are multi-processor related

47. Registers (cont.)
Serial Status Register (SSR)

48. Renesas Serial Peripheral Interface (RSPI)
Synchronous communication
Can work with as few as three wires, but more needed to access additional devices
Better method to access peripherals than parallel I/O
Common clock means you can transmit at 25.0 Mbps
Intended for very short distances (i.e. on-board)
[1]

49. SPI Details Serial Clock (RSPCK) Master Out, Slave in (MOSI)
Transmission from RX210
Master In, Slave Out (MISO)
Transmission from peripheral
Slave Select (SSLx)
Select one of the peripheral devices
We will only cover SPI in Slave Mode
[1]

50. SPI Registers Serial Peripheral Control Register (SPCR)
Slave Select Polarity (SSLP)
Serial Peripheral Pin Control Register (SPPCR)
Serial Peripheral Status (SPSR)
Serial Peripheral Data Register (SPDR)
Serial Peripheral Bit Rate Register (SPBR)
Serial Peripheral Clock Delay Register (SPCKD)

51. Serial Peripheral Control Register (SPCR)
This register controls the operating mode of the RSPI

52. Serial Peripheral Control Register (SPCR2)
This register adds to the controllability of the operating mode of the Renesas SPI

53. Slave Select Polarity (SSLP):
This register sets the polarity of the slave select lines SSL0 to SSL3 of the Renesas SPI module

54. Serial Peripheral Pin Control Register (SPPCR)
This register sets the modes of the RSPI pins

55. Serial Peripheral Status (SPSR)
This register is an indicator of the current operating status of the RSPI

56. Serial Peripheral Data Register (SPDR)
This register contains data to be transmitted and data received over the SPI channel

57. Serial Peripheral Bit Rate Register (SPBR)
The value of this register determines the rate of data transfer

58. Serial Peripheral Clock Delay Register (SPCKD)
The value of this register sets a period from the beginning of SSL signal assertion to the clock oscillations on the RSPK line

59. I2C (IIC) Inter-Integrated Circuit Bus
A two line bus for communicating data at high speeds
Multiple devices on the same bus with only one master controlling the bus
Needs pull up resistors and is kept at a digital high level when idle

60. I2C Working
Two wires:
SCL (Serial Clock): Synchronizing data transfer on the data line
SDA (Serial Data): Responsible for transferring data between devices
Together they can toggle in a controlled fashion to indicate certain important conditions that determine the status of the bus and intentions of the devices on the bus
Before any form of data transfer takes place, a device wanting to transfer data must take control of the bus (monitor the bus)

61. I2C Working (cont.) If the bus is held high, then it is free
A device may issue a START condition and take control of the bus
If a START condition is issued, no other device will transmit data on the bus (predetermined behavior for all devices)

62. I2C Working (cont.) When device is ready to give up control of the bus
It issues a STOP condition
STOP condition is one in which the SDA line gets pulled high while the SCL line is high
Other conditions: RESTART (combination of a START and STOP signal)

63. I2C Working (cont.)
Address the slave device with one byte of data which consists of a 7 bit address + 1 bit (R/W)
If this bit is low, the master wants to write to the slave device
If high, the master device wishes to read from the slave
This determines whether the next transactions are going to be read from or written to the addressed slave devices
A ninth bit (clock) is transmitted with each byte of data transmitted (ACK(Logic 0)/NACK(logic 1) bit)
The slave device must provide an ACK within the 9th cycle to acknowledge receipt of data

64. I2C Working (cont.)