1. Basic of Computer Organization
By:
Dr. Hadi Al Saadi
9/17/2018
Dr. Hadi Hassan Computer Organization

2. Dr. Hadi Hassan Computer Organization
Organization of 8086 AH AL BH BL CH CL DH DL SP BP SI DI
ALU
Flag register
Execution Unit
(EU) EU
control  CS DS SS ES
ALU Data bus
(16 bits)
Address bus (20 bits)
Instruction Queue
Bus
External bus IP
Data bus
Bus Interface Unit (BIU)
General purpose
register
Segment
9/17/2018
Dr. Hadi Hassan Computer Organization

3. Basic Program Execution Registers
Registers are high speed memory inside the CPU
Eight 16 -bit /32-bit general-purpose registers depend on processor type
Six 16-bit segment registers
Processor Status Flags ( FLAGS/ EFLAGS) and Instruction Pointer (IP/EIP) CS SS DS ES
IP/ EIP
FLAGS/ EFLAGS
16-bit Segment Registers
AX / EAX
BX/ EBX
CX/ECX
DX/EDX
8 –bit / 32-bit General-Purpose Registers FS GS
BP/ EBP
SP/ ESP
SI/ ESI
DI/ EDI
Note: E stands for Extended
9/17/2018
Dr. Hadi Hassan Computer Organization

4. General-Purpose Registers
AX, BX, CX, and DX: They can be assigned to any value you want
AX (Accumulator Register): Most of arithmetical operations are done with AX
BX (Base Register): Used to do array operations. BX is usually worked with other registers like SP to point to stacks
CX (Counter Register): Used for counter purposes
DX (Data Register). Used for storing data value
9/17/2018
Dr. Hadi Hassan Computer Organization

5. General-Purpose Registers
Used primarily for arithmetic and data movement
mov ax, 10 move constant 10 into register ax
Specialized uses of Registers
AX / EAX – Accumulator register
Automatically used by multiplication and division instructions
CX/ ECX – Counter register
Automatically used by LOOP instructions
SP/ ESP – Stack Pointer register
Used by PUSH and POP instructions, points to top of stack
SI/ ESI and DI/ EDI – Source Index and Destination Index register
Used by string instructions
BP/ EBP – Base Pointer register
Used to reference parameters and local variables on the stack
9/17/2018
Dr. Hadi Hassan Computer Organization

6. Dr. Hadi Hassan Computer Organization
16-bit Register
The general registers AX, BX, CX, and DX are 16-bit
However, they are composed from two smaller registers For example: AX
The high 8-bit is called AH, and the low 8-bit is called AL Both AH and AL can be accessed directly
However, since they altogether embodied AX
Modifying AH is modifying the high 8-bit of AX
Modifying AL is modifying the low 8-bit of AX  
AL occupy bit 0 to bit 7 of AX, AH occupy bit 8 to bit 15 of AX
9/17/2018
Dr. Hadi Hassan Computer Organization

7. Dr. Hadi Hassan Computer Organization
Extended Register
X386 processors introduce extended registers
Most of the registers, except segment registers are enhanced into 32-bit
So, we have extended registers EAX, EBX, EDX,ECX, and so on
AX is only the low 16-bit (bit 0 to 15) of EAX
There are NO special direct access to the upper 16-bit (bit 16 to 31) in extended register
9/17/2018
Dr. Hadi Hassan Computer Organization

8. General Purpose Registers
AX, BX, CX, DX 7 7
Accumulator AH BH CH DH AL BL CL DL AX BX CX DX
Base
Counter
Data
Can Be Used Separately as 1-byte Registers
AX = AH:AL
Temporary Storage to Avoid Memory Access
Faster Execution
Avoids Memory Access
Some Special uses for Certain Instructions
Note: All 8086 Microprocessor registers are 16-bit and 32-bit for and above

9. Accessing Parts of Registers
AX, BX, CX, and DX are 16-bit registers for 8086 Microprocessor
Programmers can access their 16-bit and 8-bit parts
Lower 16-bit of EAX is named AX
AX is further divided into
AL = lower 8 bits
AH = upper 8 bits
ESI, EDI, EBP, ESP have only
16-bit names for lower half
9/17/2018
Dr. Hadi Hassan Computer Organization

10. Dr. Hadi Hassan Computer Organization
Index Registers
SI and DI: Usually used to process arrays or strings:
SI (Source Index): is always pointed to the source array
DI (Destination Index): is always pointed to the destination array
9/17/2018
Dr. Hadi Hassan Computer Organization

11. Special-Purpose & Segment Registers
EIP = Extended Instruction Pointer
Contains address of next instruction to be executed
EFLAGS = Extended Flags Register
Contains status and control flags
Each flag is a single binary bit
Six 16-bit Segment Registers
Support segmented memory
Six segments accessible at a time
Segments contain distinct contents
Code
Data
Stack
9/17/2018
Dr. Hadi Hassan Computer Organization

12. Dr. Hadi Hassan Computer Organization
Segment Registers
CS, DS, ES, and SS:
CS (Code Segment Register): Points to the segment of the running program. We may NOT modify CS directly
DS (Data Segment Register): Points to the segment of the data used by the running program. You can point this to anywhere you want as long as it contains the desired data
ES (Extra Segment Register): Usually used with DI and doing pointers things. The couple DS:SI and ES:DI are commonly used to do string operations
SS (Stack Segment Register): Points to stack segment
9/17/2018
Dr. Hadi Hassan Computer Organization

13. Dr. Hadi Hassan Computer Organization
BP, SP, and IP:
BP (Base Pointer): used for preserving space to use local variables
SP (Stack Pointer): used to point the current stack
IP (Instruction Pointer ) register : contains the address of the next instruction to be executed.. It is always coupled with CS and it is NOT Modifiable. So, the couple of CS:IP is a pointer pointing to the current instruction of running program. You can NOT access CS nor IP directly
9/17/2018
Dr. Hadi Hassan Computer Organization

14. Dr. Hadi Hassan Computer Organization
Flag Register
Flag is 16-bit register that contains CPU status
It holds the value of which the programmers may need to access. This involves detecting whether the last arithmetic holds zero result or may be overflow
Intel doesn't provide a direct access to it; rather it is accessed via stack. (via POPF and PUSHF)
You can access each flag attribute by using bitwise AND operation since each status is mostly represented by just 1 bit
9/17/2018
Dr. Hadi Hassan Computer Organization

15. Processor Status and FLAGS for the 8086
Flags are classified into two types :
Status Flags: indicate status of computation and may be used to affect branching , they are bits-number : 0,2,4,6,7, and 11
Control Flags: used to enable or disable control operations , they are bits number : 8,9,and 10
9/17/2018
Dr. Hadi Hassan Computer Organization

16. Dr. Hadi Hassan Computer Organization
Flag Register cont.
Status Flags: Status of arithmetic and logical operations
C carry flag: is turned to 1 whenever the last arithmetical operation, such as adding and subtracting, has carry or borrow otherwise 0
P parity flag: It will set to 1 if the last operation (any operation) results even number of bit 1
A auxiliary flag: It is set in Binary Coded Decimal (BCD) operations
Z zero flag: used to detect whether the last operation (any operation) holds zero result
S sign flag: used to detect whether the last operation holds negative result. It is set to 1 if the highest bit (bit 7 in bytes or bit 15 in words) of the last operation is 1
9/17/2018
Dr. Hadi Hassan Computer Organization

17. Control and System flags
Overflow Flags (OF): Indicate the result during the signed numbers addition or subtraction . OF=1 , indicate the result has exceeded the capacity of destination, else (OF=0)
Control and System flags
Control the CPU operation
DF Direction Flag Auto-Increment/Decrement used for “string operations”
IF Interrupt Flag Enables Interrupts allows “fetch-execute” to be interrupted
TF Trap Flag :allows Single-Step for debugging; causes interrupt after each operation.
9/17/2018
Dr. Hadi Hassan Computer Organization

18. Dr. Hadi Hassan Computer Organization
Memory
X86 CPU only has 16-bit registers, so the maximum amount of memory that can be addressed is: = (64K)
However, after XT arrives, the memory is extended to 1 MB. That is 16 times bigger than the original
Segmentation: means the memory is divided virtually into several areas called Segment
The segment registers are 16 bit
The idea of the segmentation is NOT dividing 1 MB into 16 exact parts
Segment is an area of memory that include up to 64 K bytes (0000H~FFFFH). For intel 8086 the range of memory is only 1 M byte, this is because of its 20 bits address bus ( 2^20=1 M bytes). All real mode memory address consist of segment address plus an Offset address
9/17/2018
Dr. Hadi Hassan Computer Organization

19. Segmented Memory (x86 Style)
1- Code Segment: The code segment contains the program instructions. To execute a program , the intel fetch the instruction (opcode and operands) from the code segment. The code segment register is always used with instruction pointer to address the next instruction in a program . This combination is CS: IP . The code segment register defines the start address of the code segment and the instruction pointer locates the next instruction within the code.
9/17/2018
Dr. Hadi Hassan Computer Organization

20. Dr. Hadi Hassan Computer Organization
2- Data Segment:
Contains all the variable definitions and constant definitions of the program. The data segment register (DS) always used to hold start address of data segment and uses either BX , DI, or SI to hold the offset address which point to the data within the data segment . This combination is DS: Offset address
3- Stack Segment:
The stack is a section of memory used by CPU to store information temporarily. The CPU needs this storage area since there are a limited number of register. The main disadvantage of the stack is the access time. Stack data are referenced through the stack segment at the memory location referenced by the stack pointer (SP) or the base pointer (BP ) The combination are referred to as SS:SP or SS:BP . For example if SS=2000 H and BP = 3000H , the microprocessor address memory location 23000H for stack segment memory location.
9/17/2018
Dr. Hadi Hassan Computer Organization

21. Dr. Hadi Hassan Computer Organization
Logical and Linear Addresses
The Linear (physical) address: The (20- bit address in 8086 Microprocessor ) that is actually put on the address bin of the microprocessor. The range of this address is (00000H~FFFFFH) , this is the actual physical location in the RAM or ROM within 1 M bytes.
The Offset Address (Displacement) : The address that selects any location within the 64 KBytes memory segment , therefore an offset address range is (0000H~FFFFH).
The Logical Address: consist of a segment value and an offset address (segment address : Offset Address). Figure below shows how the segment plus offset addressing scheme selects a memory location
9/17/2018
Dr. Hadi Hassan Computer Organization

22. Dr. Hadi Hassan Computer Organization
Real Address Mode
A program can access up to six segments at any time
Code segment
Stack segment
Data segment
Extra segments (up to 3)
Each segment is 64 KB
Logical address
Segment = 16 bits
Offset = 16 bits
Linear (physical) address = 20 bits
9/17/2018
Dr. Hadi Hassan Computer Organization

23. Logical to Linear Address Translation
Linear address = Segment × 10 (hex) + Offset
Example1 :
segment = A1F0 (hex)
offset = 04C0 (hex)
logical address = A1F0:04C0 (hex)
what is the linear address?
Solution:
A1F00 (add 0 to segment in hex)
+ 04C0 (offset in hex)
A23C0 (20-bit linear address in hex)
9/17/2018
Dr. Hadi Hassan Computer Organization

24. Solution: Physical address= Segment address *10+Offset address
Example2: For a memory location of Linear address 1256A h, find the offset address for the given segment address h
Solution: Physical address= Segment address *10+Offset address
A=1256*10+offset address
Offset address= 1256A-12560=A H
A=1240*10+offset address
Offset address= 1256A-12400=16A H
Example 3: A memory has a a physical address 80FD2 h, and an offset address BFD2h, what does its segment address
Physical address= Segment address *10+Offset address
Segment address *10= Physical address- Offset address
Segment address =( 80FD2-BFD2)/10=75000/10=7500h
9/17/2018
Dr. Hadi Hassan UOP

25. Your turn . . .
What linear address corresponds to logical address 028F:0030?
Solution: 028F = (hex)
Always use hexadecimal notation for addresses
What logical address corresponds to the linear address 28F30h?
Many different segment:offset (logical) addresses can produce the same linear address 28F30h. Examples:
28F3:0000, 28F2:0010, 28F0:0030, 28B0:0430, . . .
9/17/2018
Dr. Hadi Hassan Computer Organization

26. Dr. Hadi Hassan Computer Organization
Organization of 8086
Bus Interface Unit (BIU)
Fetches the instruction and data from memory, decode the instruction to determine the type of instruction to be executed by the (EU). Machine code instruction is to be copy from memory into 6-byte queue in BIU .
Execution Unit (EU)
Execution of different arithmetic and logic instructions,(EXP,+,-,X, / ) and logic (AND, OR, XOR, and NOT), uses arithmetic logic unit (ALU) and general purpose registers (AX, BX, CX,………)
9/17/2018
Dr. Hadi Hassan Computer Organization

27. Dr. Hadi Hassan Computer OrganizationAH AL BH BL CH CL DH DL SP BP SI DI
ALU
Flag register
Execution Unit
(EU) EU
control  CS DS SS ES
ALU Data bus
(16 bits)
Address bus (20 bits)
Instruction Queue
Bus
External bus IP
Data bus
Bus Interface Unit (BIU)
General purpose
register
Segment
9/17/2018
Dr. Hadi Hassan Computer Organization

28. Instruction Execute Cycle of x86
Obtain instruction from program storage
Determine required actions and instruction size
Locate and obtain operand data
Compute result value and status
Deposit results in storage for later use
Instruction
Decode
Fetch
Operand
Execute
Writeback
Result
Infinite Cycle
9/17/2018
Dr. Hadi Hassan Computer Organization