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Optimizing Storage Electronics for Small Form Factor Drives

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Presentation on theme: "Optimizing Storage Electronics for Small Form Factor Drives"— Presentation transcript:

1 Optimizing Storage Electronics for Small Form Factor Drives
Duncan Furness Agere Storage Product Marketing

2 This market has huge potential!
CE Growth CE HDD Unit Volumes by End Application 200 Digital Video/Camera 180 Converged Device Portable Audio 160 Gaming PVR/STB 140 Upside Case 120 Unit Volumes (in millions) 100 Portable Mobile Phones Audio MP3 PDA 80 60 Priorities Digital Video Cam Portable Video Digital Still Cam 40 1. Power 2. Cost 20 Handheld Gaming Notebook 3. Capacity 2003 2004 2005 2006 2007 2008 This market has huge potential! 9/18/2018

3 Data Rates & Capacity Requirements by Format
100 GB Video 1.8” Audio Music 10 GB Pictures 1 GB 1’ & 0.85” 100 MB So, now that we know what the rates are, what the capacity points can be, clearly, we realize that there may be some gaps we need to explore. These gaps include the potential pockets where the overlap does not occur. We’ll explore these further in conjunction with other factors. What is critical from our RC IP, will be 3 items: Speed, SNR and feature set. Understanding the form factor, targeted content format, and the capacity point of each will help drive these 3 requirements, for all of the Ip we develop, RC, PA and MC. 10 MB Voice 1 MB 0.01 0.1 1 10 100 1000 Data Rate MB/s 9/18/2018

4 CE SFF Storage Requirements
Small form factor: 1”, 0.85” Removable drives 32 x 24 x 2.1 mm Priorities: Low-power consumption: Battery powered Extremely cost sensitive: $65 to $85 price with erosion High capacity: Replacement of Flash Achieve a threshold of performance 9/18/2018

5 Sample HDD Power Budget
Electromechanicaland Mechanical mW Electronics 400 Almost ½ is Electronics! A large opportunity. 10% !! 300 Camera Storage 200 Display Talk Battery Limit 100 SOC PA SPIN UP SPIN SS SEEK Cell Phone Power Budget Mechanical Manufacturing HDD Components Electromechanical Architecture Electronics Power Mgmt 9/18/2018

6 Manufacturing Processes Advances Enable Lower Power
Reduction in operating power through process shrink: Beyond 65 nM, improvement diminishes. Leakage current increases, but is three orders of magnitude smaller than operating power: Future concern Can be mitigated through Silicon on Insulator (SOI) and through triple-well CMOS design Motor controller design can benefit through use of SOI FET’s to reduce leakage power 9/18/2018

7 Lowering Power through Feature Partitioning
HDD Other IP: WiFi, UWB, LCD + Audio Amp Drivers, GPRS/GSM, UMTS/3G Video/Audio Codecs 1 PA SOC RC, HDC + IP Increasing feature density through SOC MC HDD CE 2 Mem ADC Int Repartitioned HDD DSP (HDC, uC, A/V, RC) PA Int Pwr Mgmt WLAN MC Combination of packages reduces I/O buffer requirements and reduces overall system power consumption. 9/18/2018

8 New Architectures and Requirements
READ CHANNELS Repartitioning enables fewer I/O buffer requirements: Because new interface requirements are serialized, fewer I/O buffers are needed reducing power. New Algorithm enabled by lower data rate for multimedia applications: CE device file formats are multimedia-based requiring reduced throughput on the host side, allowing for a more compact detection algorithm. New COMA modes for quiescent operation in CE devices: Sub-10 uA leakage enables competitive quiescent operation for HDD. HDC Serial interface: Parallel interfaces provide excessive bandwidth for SFF Reduce amount of I/O drivers Lower core voltages Processor speed optimization Power management: Turning off power rather than just clocks to idle blocks Need to accommodate wake-up requirements The Read Channel and HDC comprise the critical functions of the SoC 9/18/2018

9 New Architectures and Requirements
PREAMPS Lower voltages enable lower power at architecture: CE devices can do with lower voltages as a result of lower data rate requirements reducing power. Reduced data rate enables compact architecture: Reduced slew rate and capacitance requirements change architecture reducing transistor count. 9/18/2018

10 Power Mgmt: Advantage HDD
Power Consumption/GB (for files >8 MB) Peak Current Drain mA mAh/GB 300 0.60 250 0.50 200 Flash (8 MB/s) 0.40 Flash (4 MB/s) 150 HDD (1”) 0.30 HDD (sub 1”) 100 0.20 50 0.10 Current Architecture, Flash in 130 nM Process Node Distributed HDD Architecture, Flash in 65 nM Process Node Current HDD Architecture, Flash in 130 nM Process Node Distributed HDD Architecture, Flash in 65 nM Process Node Lower overall power consumption in distributed architecture enabled by data buffered into SDRAM. Lower frequency operation in HDC, COMA modes and additional savings in RC data detection algorithms to reduce power further. 9/18/2018 Source: Semico, Agere Marketing, Dec ‘03

11 Balancing the Need for Low Power and Cost
Native Speed Application Speed Select the minimum size buffer to meet the power goal and minimize cost. HDD MP3 or MPEG Buffer FAST SLOW Average HDD PD for Streaming Applications 200 MPEG4 video 180 MP3 Audio 160 110 mW Cell Battery 140 120 PD (mW) 100 80 60 40 20 1 2 3 4 5 MB of Buffer 0.25 MB MP3 1.7 MB MPEG4 9/18/2018

12 Cost Reductions SFF are moving towards serial interfaces:
Reduces #pins: SD IO, MMC – strong direction USB Integration of buffer memory into SoC: Pin reduction, package reduction Process migration when it provides a benefit: Masks are approximately 2X for 130 nM to 90 nM Die size savings need to offset NRE SoC feature partitioning: Number of packages and PCB’s reduced 9/18/2018

13 Cost Reductions Further HDD integration steps
Potentially enables a single IC approach for SFF Eliminates cost of PCB Reduces cost of head flex Allows very thin packaging of HDD Challenges: Noise on head signals Power devices on SoC Not trivial, but attractive rewards PA SOC: RC, HDC I/F MC SOC: RC, HDC I/F +PA +MC 9/18/2018

14 Channel Leadership is Key!
Capacity Drivers Advanced channel techniques: Proprietary algorithms and signal processing IP targeted at boosting effective SNR: Iterative decoding Reverse ECC Perpendicular recording with decision based baseline compensation Architectures that allow scaling from enterprise to microdrive Channel Leadership is Key! 9/18/2018

15 Takeaways Huge emerging CE market opportunity in SFF HDD’s.
Lower power enabled through component architectures, power management and manufacturing process. Average power in HDD can beat flash, with system innovation. Capacity improvements driven through read channel leadership. Cost reduction driven by partitioning, process and partnership. 9/18/2018


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