1. Introducing to Computer Architecture

2. What we will discuss today?
Architecture Content
Computer History
Classification
Chip Manufactory

3. Understand basic computer organization
Goal
Understand basic computer organization
Instruction set architecture
CPU, Cache, Memory and Optimization
Deeply explore the CPU working mechanism
How the instruction is executed: sequential and pipeline version
Help you programming
Fully understand how computer is organized and works will help you write more stable and efficient code.
…..
Method is more important!!!

4. Computer Architecture’s Changing Definition
1950s to 1960s: Computer Architecture Course: Computer Arithmetic
1970s to mid 1980s: Computer Architecture Course: Instruction Set Design, especially ISA appropriate for compilers
1990s: Computer Architecture Course: Design of CPU, memory system, I/O system, Multiprocessors, Networks
2010s: Computer Architecture Course: Multi-Core? Self adapting systems? Self organizing structures? DNA Systems/Quantum Computing? Cloud Computing ？

5. What is “Computer Architecture”?
ISA
Compiler OS
CPU
Design
Circuit
Chip
Layout
Application
Program
Coordination of many levels of abstraction
Under a rapidly changing set of forces
Design, Measurement, and Evaluation

6. Machine Abstraction Layers (cont.)
Higher level abstraction is fitter to real world.
Every level abstraction is a way of thinking.
Abstraction layers is to fill the gap between human world and the circuit world.
Human invent higher level abstraction to escape from the circuit and to meet the need of real world.
Higher level abstraction provide higher portabilility.
Every level abstraction loss some performance.
e.g. Java application vs C application
There will be more and more machine abstraction layers.

7. What is “Computer Architecture”
Instruction Set Architecture +
Machine Organization + …..

8. Instruction Set Architecture (subset of Computer Arch.)
... the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls, the logic design, and the physical implementation – Amdahl, Blaaw, and Brooks, 1964

9. The Instruction Set: a Critical Interface
software
instruction set
hardware

10. Example ISAs (Instruction Set Architectures)
Digital Alpha (v1, v3)
HP PA-RISC (v1.1, v2.0)
Sun Sparc (v8, v9)
SGI MIPS (MIPS I, II, III, IV, V)
Intel (8086,80286,80386, ,Pentium, MMX, ...)
IA64
EM64T

11. Ways in which these components are interconnected
Machine Organization
Capabilities & Performance Characteristics of Principal Functional Units
(e.g., Registers, ALU, Shifters, Logic Units, ...)
Ways in which these components are interconnected
Information flows between components
Logic and means by which such information flow is controlled.
Choreography of FUs to realize the ISA
Register Transfer Level (RTL) Description
Logic Designer's View
ISA Level
FUs & Interconnect

12. Sample Organization: It’s all about communication
Pentium III Chipset
Proc
Caches
Busses
Memory
I/O Devices:
Controllers
adapters
Disks
Displays
Keyboards
Networks
All have interfaces & organizations

13. Forces on Computer Architecture
Technology
Programming
Languages
Applications
Computer
Architecture
Cleverness
Operating
Systems
History

14. Computer History Who Cares? Ancient
To understand anything that changes quickly, must look to the past
Ancient
Big mainframes
Von Neumann saw a need for at most 10 machines in the U.S.

15. About 1,800 Years Later Never finished Charles Babbage
Analytical Engine
Started in 1834
No Hertz Rating
Never finished

16. The Zuse Z3 & Z4
Z1 / 1938,
Z3 / 1941: First freely programmable machines in the world
Z3 and its
successor Z4 can be seen at the „Deutsches Museum“!

17. Modern Computer History
Eckert and Mauchly
1st working electronic computer (1946)
18,000 Vacuum tubes
1,800 instructions/sec
3,000 ft3

18. Computer History EDSAC 1 (1949) Maurice Wilkes
1st stored program computer
650 instructions/sec
1,400 ft3
EDSAC 1 (1949)

19. Developed 1946－1952 by von Neumann
The IAS machine
Developed 1946－1952 by von Neumann
First machine based on his design principle
Institute for Advanced Studies computer

20. Instructions / Program
Von Neumann – Overview
Instructions / Program
Main
Memory
Arithmetic
Unit
Control
Unit PC AC IR SR
Addresses
Input/Output
Unit
E.g. Storage

21. Still the dominant architecture in current systems
Von Neumann – Today
Still the dominant architecture in current systems
Used in all popular systems / chips
Only minor modifications
Control und Arithmetic unit combined Result: CPU (Central Processing Unit)
New memory paths between memory and I/O Direct Memory Access (DMA)
Additions to the concept
Multiple arithmetic units / Multiple CPUs
Parallel processing

22. IBM 360 Series First planned “family” of computers(1964)
The System/360 and its successors dominated the large computer market

23. PDP-8 Announced in 1965 Designed by DEC
The first commercial minicomputer
A breakthrough in low-cost design

24. Cray-1
Announced in 1976
The first commercial vector supercomputer

25. Microprocessor History
4-Bit, 8-Bit Processors
Intel 4004 (~1971)
Intel 8008
16-Bit Processors
Texas Instruments TMS 9900 (~1977)
Intel 8086
Zilog Z8000
Motorola MC68000
National Semiconductor NS16016
(~ )

26. Intel 4004 Die Photo Introduced in 1970 2,250 transistors 12 mm2
First microprocessor
2,250 transistors
12 mm2
108 KHz

27. Intel 4004 – First Microcomputer

28. Microprocessor History
16/32-bit Processors (external 16-bit Bus, internal 32 Bit Structure)
Motorola MC68010
National Semiconductor NS16032
Additional Functionality on the Chip
Direct Memory Access (DMA) (Intel 80186)
Virtual memory management (MC68010, Intel 80286)
Optional Coprocessor (Intel 8086/80286, NS16032)
Extended Address Space

29. Microprocessor History
32-bit Processors
CISC Processors
Motorola MC680x0
Intel i386 / i486 / Pentium
National Semiconductor NS32x32
Concept of a Processor Family
Binary Compatibility
Compatible with 16 Bit Processors
RISC Processors
Advanced Micro Devices Am29000 (~1987)
Sun Microsystems SPARC
MIPS technologies MIPS R2000 / MIPS R3000

30. Pentium 4 (55 Million Transistors)

31. Microprocessor History
64/32-bit Processors
SUN Microsystems SuperSPARC
Motorola 88110
IBM, Motorola PowerPC 601 (MPC601)
“Modern” Processors
64-bit Structure
Internal Parallelism
Instruction pipelining
Arithmetic Pipelining
Instruction and Data Caches
Advanced Memory and Peripheral Connections

32. Itanium (25.4 Million Transistors)

33. History of Computer Architecture
4 Generations (identified by logic technology)
Tubes
Transistors
Integrated Circuits
VLSI (very large scale integration)

34. Moore is co-founder of Intel.
Moore’s Law
“Transistor density doubles every 18 months”
Moore is co-founder of Intel.
60 % increase per year
Exponential growth
PC costs decline.
PCs are building bricks of all future systems.

35. Bit Level Parallelism (upto mid 80’s)
4 bit microprocessors replaced by 8 bit, 16 bit, 32 bit etc.
doubling the width of the datapath reduces the number of cycles required to perform a full 32-bit operation
mid 80’s reap benefits of this kind of parallelism (full 32-bit word operations combined with the use of caches)

36. Instruction Level Parallelism (mid 80’s to mid 90’s)
Basic steps in instruction processing (instruction decode, integer arithmetic, address calculations, could be performed in a single cycle)
Pipelined instruction processing
Reduced instruction set (RISC)
Superscalar execution
Branch prediction

37. Thread/Process Level Parallelism (mid 90’s to present)
On average control transfers occur roughly once in five instructions, so exploiting instruction level parallelism at a larger scale is not possible
Use multiple independent “threads” or processes
Concurrently running threads, processes

38. classifies computer architectures according to:
Flynn’s Taxonomy
classifies computer architectures according to:
Number of instruction streams it can process at a time
Number of data elements on which it can operate simultaneously
Data Streams
Single Multiple
Single
SISD
SIMD
Instruction Streams
MISD
MIMD
Multiple

39. MISD

40. Grand Challenge Applications
Important scientific & engineering problems identified by U.S. High Performance Computing & Communications Program (’92)

42. Integrated Circuit

43. Integrated Circuit Costs
Die cost = Wafer cost
Dies per Wafer * Die yield
Dies per wafer =  * ( Wafer_diam / 2)2 –  * Wafer_diam – Test dies  Wafer Area
Die Area  2 * Die Area Die Area
Die Yield = Wafer yield 
{ 1+
Defects_per_unit_area * Die_Area  }
Die Cost is goes roughly with (die area)3 or (die area)4

44. Logic capacity is no longer a problem Die yield is relative high
Current Status
Logic capacity is no longer a problem
Die yield is relative high
So, the problem is how to fully utilize the logic capacity!
Increase clock
Different design
Hyper-threading
Multi-core
Virtualization

45. Parallel Processing Institute