1. Lecture 7 Fault Simulation
Problem and motivation
Fault simulation algorithms
Serial
Parallel
Deductive
Concurrent
Random Fault Sampling
Summary
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VLSI Test: Lecture 7

2. Problem and Motivation
Fault simulation Problem: Given
A circuit
A sequence of test vectors
A fault model
Determine
Fault coverage - fraction (or percentage) of modeled faults detected by test vectors
Set of undetected faults
Motivation
Determine test quality and in turn product quality
Find undetected fault targets to improve tests
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VLSI Test: Lecture 7

3. Fault simulator in a VLSI Design Process
Verification
input stimuli
Verified design
netlist
Fault simulator
Test vectors
Modeled
fault list
Remove
tested faults
Test
compactor
Delete
vectors
Fault
coverage ?
Low
Test
generator
Add vectors
Adequate
Stop
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VLSI Test: Lecture 7

4. Fault Simulation Scenario
Circuit model: mixed-level
Mostly logic with some switch-level for high-impedance (Z) and bidirectional signals
High-level models (memory, etc.) with pin faults
Signal states: logic
Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits
Four states (0, 1, X, Z) for sequential MOS circuits
Timing:
Zero-delay for combinational and synchronous circuits
Mostly unit-delay for circuits with feedback
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VLSI Test: Lecture 7

5. Fault Simulation Scenario (continued)
Mostly single stuck-at faults
Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use
Equivalence fault collapsing of single stuck-at faults
Fault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosis
Fault sampling -- a random sample of faults is simulated when the circuit is large
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VLSI Test: Lecture 7

6. Fault Simulation Algorithms
Serial
Parallel
Deductive
Concurrent
Differential
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VLSI Test: Lecture 7

7. Serial Algorithm
Algorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault in the fault list:
Modify netlist by injecting one fault
Simulate modified netlist, vector by vector, comparing responses with saved responses
If response differs, report fault detection and suspend simulation of remaining vectors
Advantages:
Easy to implement; needs only a true-value simulator, less memory
Most faults, including analog faults, can be simulated
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VLSI Test: Lecture 7

8. Serial Algorithm (Cont.)
Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuits
Alternative: Simulate many faults together
Test vectors
Fault-free circuit
Comparator
f1 detected?
Circuit with fault f1
Comparator
f2 detected?
Circuit with fault f2
Comparator
fn detected?
Circuit with fault fn
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VLSI Test: Lecture 7

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VLSI Test: Lecture 7

10. Example
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VLSI Test: Lecture 7

11. Parallel Fault Simulation
Compiled-code method; best with two-states (0,1)
Exploits inherent bit-parallelism of logic operations on computer words
Storage: one word per line for two-state simulation
Multi-pass simulation: Each pass simulates w-1 new faults, where w is the machine word length
Speed up over serial method ~ w-1
Not suitable for circuits with timing-critical and non-Boolean logic F9 F8 F7 F6 F5 F4 F3 F2 F1
F F
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VLSI Test: Lecture 7

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VLSI Test: Lecture 7

13. Parallel Fault Sim. Example
Bit 0: fault-free circuit
Bit 1: circuit with c s-a-0
Bit 2: circuit with f s-a-1
c s-a-0 detected a b e c
s-a-0 g d f
s-a-1
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 7

14. Fault-Tolerant Digital System Design
Fault Injection for parallels fault simulation 1
6,7 week
Fault-Tolerant Digital System Design

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VLSI Test: Lecture 7

16. Deductive Fault Simulation
One-pass simulation
Each line k contains a list Lk of faults detectable on k
Following true-value simulation of each vector, fault lists of all gate output lines are updated using set-theoretic rules, signal values, and gate input fault lists
PO fault lists provide detection data
At each of the primary inputs generate the list of faults that can be detected by the test vector
Use these lists to generate the lists at other nodes by “appropriate” operations on these lists
Limitations:
Set-theoretic rules difficult to derive for non-Boolean gates
Gate delays are difficult to use
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 7

17. Fault-Tolerant Digital System Design
Fault Lists
In deductive c1
a1,c1
b1,c1
a0,b0,c0
Fault lists propagation
In deductive fault
simulator
Is the set of faults not in LB
6,7 week
Fault-Tolerant Digital System Design

18. Deductive Fault Sim. Example
Notation: Lk is fault list for line k
kn is s-a-n fault on line k
Le = La U Lc U {e0}
= {a0 , b0 , c0 , e0} 1
{a0} a
{b0 , c0} 1 e b 1 1
{b0} c g f d
Lg = (Le Lf ) U {g0}
= {a0 , c0 , e0 , g0} U
{b0 , d0}
{b0 , d0 , f1}
Faults detected by
the input vector
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 7

19. Fault-Tolerant Digital System Design
Two valued Deductive Simulation 1 or 1
Is the set of faults not in LB
6,7 week
Fault-Tolerant Digital System Design

20. Fault-Tolerant Digital System Design
6,7 week
Fault-Tolerant Digital System Design

21. Fault-Tolerant System Design
4 Week
Fault-Tolerant System Design

22. Fault-Tolerant Digital System Design
Example 5.1
Example 5.1 1 1 1 1 1 1 1 1 1 1
Test Vector
6,7 week
Fault-Tolerant Digital System Design

23. Fault-Tolerant Digital System Design
6,7 week
Fault-Tolerant Digital System Design

24. Deductive Fault Simulation (example)
La = {a1} Lb = {b0} Lc = {c1} Ld = {d0} Le = {e1} a i 1 b 1 f c
Lfp = Lb’  Lc = {c1}
Lf = {c1, f1}
Lgp = (Ld  Le’) = {d0}
Lg = {d0, g1}
Lhp = (Lf  Lg), Lhp = 
Lh = {h0}
Lip = La’  Lh , Lip = {h0}
Li = {h0, i0} h 1 1 d g e

25. Deductive Fault Simulation (example contd.)
La = {a1} Lb = {b0} Lc = {c0} Ld = {d0} Le = {e1} a i 1 b 1 f 1 c
Lfp = Lb  Lc = { b0, c0}
Lf = {b0, c0, f0}
Lgp = (Ld  Le’) = {d0}
Lg = {d0, g1}
Lhp = (Lf ‘ Lg) ={ d0 , g1 }
Lhp = {d0,g1} , Lh = {d0,g1,h0}
Lip = La’  Lh , Lip = {d0, g1,h0}
Li = {d0, g1, h0, i0} h 1 1 1 d g e

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VLSI Test: Lecture 7

27. Concurrent Fault Simulation
Event-driven simulation of fault-free circuit and only those parts of the faulty circuit that differ in signal states from the fault-free circuit.
A list per gate containing copies of the gate from all faulty circuits in which this gate differs. List element contains fault ID, gate input and output values and internal states, if any.
All events of fault-free and all faulty circuits are implicitly simulated.
Faults can be simulated in any modeling style or detail supported in true-value simulation (offers most flexibility.)
Faster than other methods, but uses most memory.
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 7

28. Conc. Fault Sim. Example a0 b0 c0 e0 a0 b0 c0 e0 b0 d0 f1 g0 f1 d0 a e1 1 1 1 1 a 1 1 1 e b 1 c 1 1 g 1 a0 b0 c0 e0 d f 1 1 1 1 b0 d0 f1 g0 1 f1 d0 1 1
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 7

29. Fault-Tolerant Digital System Design
Fault-Lists (Bad-gates)
In concurrent Fault
Simulation
Lg={a0,c0,e0,g0}
6,7 week
Fault-Tolerant Digital System Design

30. Fault-Tolerant Digital System Design
Event processing and convergence in concurrent fault simulation
The processing of the ( ) good-event
at a is not complete
6,7 week
Fault-Tolerant Digital System Design

31. Fault-Tolerant Digital System Design
Complete fault-lists (bad gates)
Bade-gate divergence in concurrent fault simulation
6,7 week
Fault-Tolerant Digital System Design

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VLSI Test: Lecture 7

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VLSI Test: Lecture 7

34. Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 7

35. Fault-Tolerant Digital System Design
6,7 week
Fault-Tolerant Digital System Design

36. Fault-Tolerant Digital System Design
Critical Path Tracing
6,7 week
Fault-Tolerant Digital System Design

37. Fault-Tolerant Digital System Design
Example of Critical path tracing in fanout-free circuit
6,7 week
Fault-Tolerant Digital System Design

38. Fault-Tolerant Digital System Design
S-a-0
S-a-0
S-a-1
S-a-0
S-a-0
6,7 week
Fault-Tolerant Digital System Design

39. Fault-Tolerant Digital System Design
Example of Self masking B S-a-0 x
S-a-0 1 1
6,7 week
Fault-Tolerant Digital System Design

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VLSI Test: Lecture 7

41. Routh’s TEST-DETECT Algorithm
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VLSI Test: Lecture 7

42. Fault Sampling
A randomly selected subset (sample) of faults is simulated.
Measured coverage in the sample is used to estimate fault coverage in the entire circuit.
Advantage: Saving in computing resources (CPU time and memory.)
Disadvantage: Limited data on undetected faults.
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VLSI Test: Lecture 7

43. Motivation for Sampling
Complexity of fault simulation depends on:
Number of gates
Number of faults
Number of vectors
Complexity of fault simulation with fault sampling depends on:
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VLSI Test: Lecture 7

44. Random Sampling Model Detected Undetected fault fault All faults with
a fixed but
unknown
coverage
Random
picking
Np = total number of faults
(population size)
C = fault coverage (unknown)
C Np = Actual Detectable Faults
Ns = sample size
Ns << Np
c = sample coverage
(a random variable)
x Ns = # of sample faults detected by given vectors
X = value of c determined from
sample fault simulation
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VLSI Test: Lecture 7

45. Number of ways obtaining sample of size Ns
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VLSI Test: Lecture 7

46. Probability Density of Sample Coverage, c
(x--C )2
s 2
p (x ) = Prob(x < c < x +dx ) = e
s (2 p) 1/2
C (1 - C)
Variance, s 2 = Ns
Sampling
Error x-C s s
p (x )
Mean = C x
C -3s x
C +3s
1.0 C
Sample coverage
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VLSI Test: Lecture 7

47. Sampling Error Bounds C (1 - C ) | x - C | = 3 [ -------------- ] 1/2Ns
Solving the quadratic equation for C, we get the
3-sigma (99.7% confidence) coverage estimate:
4.5
C 3s = x [ Ns x (1 - x )]1/2 Ns
Where Ns is sample size and x is the measured fault
coverage in the sample.
Example: A circuit with 39,096 faults has an actual
fault coverage of 87.1%. The measured coverage in
a random sample of 1,000 faults is 88.7%. The above
formula gives an estimate of 88.7% 3%. CPU time for sample simulation was about 10% of that for all faults.
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VLSI Test: Lecture 7

48. Summary Fault simulator is an essential tool for test development.
Concurrent fault simulation algorithm offers the best choice.
For restricted class of circuits (combinational and synchronous sequential with only Boolean primitives), differential algorithm can provide better speed and memory efficiency (Section )
For large circuits, the accuracy of random fault sampling only depends on the sample size (1,000 to 2,000 faults) and not on the circuit size. The method has significant advantages in reducing CPU time and memory needs of the simulator.
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VLSI Test: Lecture 7

49. homeworks
5-1, 5-17,5-18, 5-20 , 5-23, 5-25