1. Intro to Verilog HDL Combinational Blocks
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2. Outline Introduction: Verilog overview Simulation and Synthesis
Modules and Primitives
Styles
Structural Descriptions
Data Types
Delay
Behavioral Constructs
Compiler Directives
Simulation and Testbenches
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3. Verilog Overview Verilog is a concurrent language
Aimed at modeling hardware — optimized for it!
Typical of hardware description languages (HDLs), it:
provides for the specification of concurrent activities
stands on its head to make the activities look like they happened at the same time
Why?
allows for intricate timing specifications
A concurrent language allows for:
Multiple concurrent “elements”
An event in one element to cause activity in another. (An event is an output or state change at a given time)
based on interconnection of the element’s ports
Further execution to be delayed
until a specific event occurs
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4. Simulation of Digital Systems
What do you do to test a software program you write?
Give it some inputs, and see if it does what you expect
When done testing, is there any assurance the program is bug free? — NO!
But, to the extent possible, you have determined that the program does what you want it to do
Simulation tests a model of the system you wish to build
Is the design correct? Does it implement the intended function correctly? For instance, is it a UART
Stick in a byte and see if the UART model shifts it out correctly
Also, is it the correct design?
Might there be some other functions the UART could do?
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5. Simulation of Digital Systems
Simulation checks two properties
functional correctness — is the logic correct
correct design, and design correct
timing correctness — is the logic/interconnect timing correct
e.g. are the set-up times met?
It has all the limitations of software testing
Have I tried all the cases?
Have I exercised every path? Every option?
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6. Modern Design Methodology
Simulation and Synthesis are components of a design methodology
always ….
Synthesis
gates, gates, gates, …
Technology Mapping
Synthesizable Verilog
Place and Route
LE1
LE2
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7. Verilog Levels of Abstraction
Gate modeling (Structural modeling)
the system is represented in terms of primitive gates and their interconections
NANDs, NORs, …
Behavioral modeling
the system is represented by a program-like language D
always
@posedge clock
Q = #5 D
gate-level model
behavioral model Q
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8. Representation: Structural Models
Are built from gate primitives and/or other modules
They describe the circuit using logic gates — much as you would see in an implementation of a circuit.
Identify:
Gate instances, wire names, delay from a or b to f.
This is a multiplexor — it selects one of n inputs (2 here) and passes it on to the output
module MUX (f, a, b, sel);
output f;
input a, b, sel;
and #5 g1 (f1, a, nsel),
g2 (f2, b, sel);
or #5 g3 (f, f1, f2);
not g4 (nsel, sel);
endmodule a b f
sel
f =
a • sel’ + b • sel
nsel f2 f1
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9. Module Declaration Identifiers - must not be keywords! Ports
First example of signals
Scalar: e. g., E_n
Vector: e. g., A[1:0], A[0:1], D[3:0], and D[0:3]
Range is MSB to LSB
Can refer to partial ranges - D[2:1]
Type: defined by keywords
input
output
inout (bi-directional)
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10. Module Instantiation Example Decoder 2 to 4 with enable
module C_2_4_decoder_with_enable (A, E_n, D) ;
input [1:0] A ;
input E_n ;
output [3:0] D ;
wire A0_n, A1_n;
not go(A0_n, A[0]), g1(A1_n, A[1]);
and g3(D[0], E_n,A0_n, A1_n),
g4(D[1],E_n, A[0], A1_n),
g5(D[2],E_n, A0_n, A[1]),
g6(D[3], E_n,A[0], A[1]);
endmodule
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11. Module Instantiation Example
module C_4_16_decoder_with_enable (A, E_n, D) ;
input [3:0] A ;
input E_n ;
output [15:0] D ;
wire [3:0] S;
C_2_4_decoder_with_enable DE (A[3:2], E_n, S);
C_2_4_decoder_with_enable D0 (A[1:0], S [0], D[3:0]);
C_2_4_decoder_with_enable D1 (A[1:0], S [1], D[7:4]);
C_2_4_decoder_with_enable D2 (A[1:0], S [2], D[11:8]);
C_2_4_decoder_with_enable D3 (A[1:0], S [3], D[15:12]);
endmodule
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12. Style Example - Structural
module full_add (A, B, CI, S, CO) ;
input A, B, CI ;
output S, CO ;
wire N1, N2, N3;
half_add HA1 (A, B, N1, N2),
HA2 (N1, CI, S, N3);
or P1 (CO, N3, N2);
endmodule
module half_add (X, Y, S, C); input X, Y ; output S, C ; xor (S, X, Y) ; and (C, X, Y) ; endmodule
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13. Style Example - RTL/Dataflow
module fa_rtl (A, B, CI, S, CO) ; //aka Data flow
input A, B, CI ;
output S, CO ;
assign S = A ^ B ^ CI; //continuous assignment
assign CO = A & B | A & CI | B & CI; //continuous assignment
endmodule
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14. Style Example - Behavioral
module fa_bhv (A, B, CI, S, CO) ;
input A, B, CI ;
output S, CO ;
reg S, CO; // required to “hold” values between events.
or B or CI) //;
begin
S <= A ^ B ^ CI; // procedural assignment
CO <= A & B | A & CI | B & CI; // procedural assignment
end
endmodule
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15. Instantiation Connections
By position association
module C_2_4_decoder_with_enable (A, E_n, D);
C_2_4_decoder_with_enable DX (X[3:2], W_n, word);
A  X[3:2], E_n  W_n, wordD
By name association
C_2_4_decoder_with_enable DX (.E_n(W_n), .A(X[3:2]), .D(word));
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16. Connections Empty Port Connections
module C_2_4_decoder_with_enable (A, E_n, D);
C_2_4_decoder_with_enable DX (X[3:2], , word);
E_n is at high-impedance state (z)
C_2_4_decoder_with_enable DX (X[3:2], W_n ,);
Outputs D[3:0] unused.
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17. Number Representation
Examples:
6’b010_111 gives
8'b0110 gives
8’b1110 gives
4'bx01 gives xx01
16'H3AB gives
24 gives 0…
5'O36 gives 11110
16'Hx gives xxxxxxxxxxxxxxxx
8'hz gives zzzzzzzz
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18. Representation: Gate-Level Models
Need to model the gate’s:
Function
Delay
Generally, HDLs have built-in gate-level primitives
Verilog has NAND, NOR, AND, OR, XOR, XNOR, BUF, NOT, and some others
The gates operate on input values producing an output value
typical Verilog gate instantiation is
and #delay instance-name (out, in1, in2, in3, …);
optional
“many”
and #5 g1 (f1, a, nsel);
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19. Four-Valued Logic Verilog Logic Values
The underlying data representation allows for any bit to have one of four values
1, 0, x (unknown), z (high impedance)
x : e.g. the state of change
z : e.g. output of a tri-state gate.
What basis do these have in reality?
0, 1 … no question
z … A tri-state gate drives either a zero or one on its output. If it’s not doing that, its output is high impedance (z). Tri-state gates are real devices and z is a real electrical affect.
x … not a real value. There is no real gate that drives an x on to a wire. x is used as a debugging aid. x means the simulator can’t determine the answer and so maybe you should worry!
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20. Operators Arithmetic (binary: +, -,*,/,%); (unary: +, -)
Bitwise (~, &,|,^,~^,^~)
Reduction (&,~&,|,~|,^,~^,^~)
Logical (!,&&,||,==,!=)
Relational (<,<=,>,>=)
Shift (>>,<<)
Conditional ? :
Concatenation and Replications {,} {int{ }}
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21. Examples
module Reduction (A, Y1, Y2, Y3, Y4, Y5, Y6); input [3:0] A; output Y1, Y2, Y3, Y4, Y5, Y6; assign Y1=&A; //reduction AND assign Y2=|A; //reduction OR assign Y3=~&A; //reduction NAND assign Y4=~|A; //reduction NOR assign Y5=^A; //reduction XOR assign Y6=~^A; //reduction XNOR endmodule
Verilog has six reduction operators, these operators accept a single vectored (multiple bit) operand, performs the appropriate bit-wise reduction on all bits of the operand, and returns a single bit result. For example, the four bits of A are ANDed together to produce Y1. Assign
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22. Expression Bit Widths Depends on:
widths of operands and
types of operators
Verilog fills in smaller-width operands by using zero extension.
Final or intermediate result width may increase expression width
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23. Expression Bit Widths
Unsized constant number- same as integer (usually 32)
Sized constant number - as specified
x op y where op is +, -, *, /, %, &, |, ^, ^~:
Arithmetic binary and bitwise
Bit width = max (width(x), width(y))
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24. Expression Bit Widths (continued)
op x where op is +, -
Arithmetic unary
Bit width = width(x)
Carry can be captured if final result width > width(x)
op x where op is ~
Bitwise negation
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25. Expression Bit Widths (continued)
x op y where op is ==, !==, &&, ||, >, >=, <, <= or op y where op is !, &, |, ^, ~&, ~|, ~^
Logical, relational and reduction
Bit width = 1
x op y where op is <<, >>
Shift
Bit width = width(x)
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26. Expression Bit Widths (continued)
x ? y : z
Conditional
Bit width = max(width(y), width(z))
{x, …, y}
Concatenation
Bit width = width(x) + … + width(y)
{x{y, …, z}}
Replication
Bit width = x * (width(y) + … + width(z))
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27. Expressions with Operands Containing x or z
Arithmetic
If any bit is x or z, result is all x’s.
Divide by 0 produces all x’s.
Relational
If any bit is x or z, result is x.
Logical
== and != If any bit is x or z, result is x.
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28. Expressions with Operands Containing x or z
Bitwise
Defined by tables for 0, 1, x, z operands.
Reduction
Defined by tables as for bitwise operators.
Shifts
z changed to x. Vacated positions zero filled.
Conditional
If conditional expression is ambiguous (e.g., x or z), both expressions are evaluated and bitwise combined as follows: f(1,1) = 1, f(0,0) = 0, otherwise x.
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29. Structural vs Behavioral Models
Structural model
Just specifies primitive gates and wires
i.e., the structure of a logical netlist
You basically know how to do this now.
Behavioral model
More like a procedure in a programming language
Still specify a module in Verilog with inputs and outputs...
...but inside the module you write code to tell what you want to have happen, NOT what gates to connect to make it happen
i.e., you specify the behavior you want, not the structure to do it
Why use behavioral models
For testbench modules to test structural designs
For high-level specs to drive logic synthesis tools
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30. How do behavioral models fit in?
How do they work with the event list and scheduler?
Initial (and always) begin executing at time 0 in arbitrary order
They execute until they come to a “#delay” operator
They then suspend, putting themselves in the event list 10 time units in the future (for the case at the right)
At 10 time units in the future, they resume executing where they left off.
module testAdd(a, b, sum, cOut);
input sum, cOut;
output a, b;
reg a, b;
Add a1 (a, b , sum, cOut);
initial begin
a = 0; b = 0;
#10 b = 1;
#10 a = 1;
#10 b = 0;
end
endmodule
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31. Two initial statements?…
initial begin
a = 0; b = 0;
#5 b = 1;
#13 a = 1;
end
#10 out = 0;
#8 out = 1; 1 10 18 a b
out
Things to note
Which initial statement starts first?
What are the values of a, b, and out when the simulation starts?
These appear to be executing concurrently (at the same time). Are they?
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32. Two initial statements?…
initial begin
a = 0; b = 0;
#5 b = 1;
#13 a = 1;
end
#10 out = 0;
#8 out = 1; 1 a 1 b 1
out 10 18
They start at same time
Things to note
Which initial statement starts first?
What are the initial values of a, b, and out when the simulation starts?
These appear to be executing concurrently (at the same time). Are they?
Undefined (x)
Not necessarily
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33. Behavioral Modeling Procedural statements are used
Statements using “initial” and “always” Verilog constructs
Can specify both combinational and sequential circuits
Normally don’t think of procedural stuff as “logic”
They look like C: mix of ifs, case statements, assignments …
… but there is a semantic interpretation to put on them to allow them to be used for simulation and synthesis (giving equivalent results)
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34. Behavioral Constructs
Behavioral descriptions are introduced by initial and always statements
Points:
They all execute concurrently
They contain behavioral statements like if-then-else, case, loops, functions, …
initial
always
Starts when simulation starts
Execute once and stop
Continually loop— while (sim. active) do statements;
Not used in synthesis
Used in synthesis
Statement
Starts
How it works
Use in Synthesis?
Looks like
begin …
end
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35. Statements, Registers and Wires
Define storage, can be more than one bit
Can only be changed by assigning value to them on the left-hand side of a behavioral expression.
Wires (actually “nets”)
Electrically connect things together
Can be used on the right-hand side of an expression
Thus we can tie primitive gates and behavioral blocks together!
Statements
left-hand side = right-hand side
left-hand side must be a register
Four-valued logic
Multi-bit registers and wires
module silly (q, r);
reg [3:0] a, b;
wire [3:0] q, r;
always begin …
a = (b & r) | q;
q = b;
end
endmodule
Logic with registers and wires
Can’t do — why?
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36. Behavioral Statements
if-then-else
What you would expect, except that it’s doing 4-valued logic. 1 is interpreted as True; 0, x, and z are interpreted as False
case
What you would expect, except that it’s doing 4-valued logic
If “selector” is 2 bits, there are 42 possible case-items to select between
There is no break statement — it is assumed.
Funny constants?
Verilog allows for sized, 4-valued constants
The first number is the number of bits, the letter is the base of the following number that will be converted into the bits.
8’b00x0zx10
if (select == 1)
f = in1;
else f = in0;
case (selector)
2’b00: a = b + c;
2’b01: q = r + s;
2’bx1: r = 5;
default: r = 0;
endcase
assume f, a, q, and r are registers for this slide
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37. Behavioral Statements
Loops
There are restrictions on using these for synthesis — don’t.
They are mentioned here for use in test modules and behavioral models not intended for synthesis
Two main ones — for and while
Just like in C
There is also repeat and forever
reg [3:0] testOutput, i; …
for (i = 0; i <= 15; i = i + 1) begin
testOutput = i;
#20;
end
reg [3:0] testOutput, i; …
i = 0;
while (i <= 15)) begin
testOutput = i;
#20 i = i + 1;
end
Important: Be careful with loops. Its easy to create infinite loop situations.
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38. Test Module, continued Bit Selects and Part Selects
This expression extracts bits or ranges of bits or a wire or register
module top;
wire w0, w1, w2, w3;
testgen t (w0, w1, w2, w3);
design d (w0, w1, w2, w3);
end
The individual bits of register i are made available on the ports. These are later connected to individual input wires in module design.
module testgen (i[3], i[2], i[1], i[0]);
reg [3:0] i; output [3:0] i;
always
for (i = 0; i <= 15; i = i + 1)
#20;
endmodule
module design (a, b, c, d);
input a, b, c, d;
…….
end
module testgen (i);
reg [3:0] i; output [3:0] i;
always
for (i = 0; i <= 15; i = i + 1)
#20;
endmodule
module top;
wire [3:0] w;
testgen t (w);
design d (w[0], w[1], w[2], w[3]);
end
Alternate:
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39. FAQs: behavioral model execution
How does an always or initial statement start
That just happens at the start of simulation — arbitrary order
Once executing, what stops it?
Executing either a or wait(FALSE).
All always blocks need to have at least one of these. Otherwise, the simulator will never stop running the model -- (it’s an infinite loop!)
How long will it stay stopped?
Until the condition that stopped it has been resolved
#delay … until the delay time has been reached
@(var) … until var changes
wait(var) … until var becomes TRUE
Does time pass when a behavioral model is executing?
No. The statements (if, case, etc) execute in zero time.
Time passes when the model stops for or wait.
Will an always stop looping?
No. But an initial will only execute once.
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40. Activity Control Overview Constructs for Activity Control
Conditional operator
case statement
if … else statement
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41. Conditional Operator ? … :
Same as for use in continuous assignment statement for net types except applied to register types
Example:
clock)
Q <= S ? A : B //combined DFF and 2-to-1 MUX
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42. Case Statement case Syntax: case_statement ::= case (expression)
case_item {case_item} endcase
| casex (expression)
| casez (expression)
case_item ::= expression {,expression} : statement_or_null |default [:] statement_or_null
statement_or_null ::= statement | ;
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43. case Statement
Requires complete bitwise match over all four values so expression and case item expression must have same bit length
Example: x)
begin
reg[1:0] state;
case (state)
2’b00: next_state <= s1;
2’b01: next_state <= s2;
2’b10: if x next_state <= s0;
else next_state <= s1;
default next_state = 1’bxx;
endcase
end
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44. Using a case statement Truth table method Concatenation
List each input combination
Assign to output(s) in each case item.
Concatenation
{a, b, c} concatenates a, b, and c together, considering them as a single item
Example
a = 4’b0111
b = 6’b 1x0001
c = 2’bzx
then {a, b, c} = 12’b01111x0001zx
module fred (f, a, b, c);
output f;
input a, b, c;
reg f;
(a or b or c)
case ({a, b, c})
3’b000: f = 1’b0;
3’b001: f = 1’b1;
3’b010: f = 1’b1;
3’b011: f = 1’b1;
3’b100: f = 1’b1;
3’b101: f = 1’b0;
3’b110: f = 1’b0;
3’b111: f = 1’b1;
endcase
endmodule
Important: every control path is specified
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45. Two inputs, Three outputs
reg [1:0] newJ;
reg out;
input i; input [1:0] j;
or j)
case (j)
2’b00: begin
newJ = (i == 0) ? 2’b00 : 2’b01;
out = 0;
end
2’b01 : begin
newJ = (i == 0) ? 2’b10 : 2’b01;
out = 1;
2’b10 : begin
newJ = 2’b00;
default: begin
out = 1'bx;
endcase
Works like the C conditional operator.
(expr) ? a : b;
If the expr is true, then
the resulting value is a, else it’s b.
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46. casex Statement
Requires bitwise match over all but positions containing x or z; executes first match encountered if multiple matches.
Example:
begin
casex (code)
2’b0x: control <= 8’b ; //same for 2’b0z
2’b10: control <= 8’b ;
2’b11: control <= 8’b ;
default control <= 8b’xxxxxxxx;
endcase
end
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47. casez Statement
Requires bitwise match over all but positions containing z or ? (? is explicit don’t care); executes first match encountered if multiple matches.
Example:
reg [1:0] code;
begin
casez (code)
2’b0z: control <= 8’b ;
2’b1?: control <= 8’b ;
default control <= 8b’xxxxxxxx;
endcase
end
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48. Conditional (if … else) Statement Example
or b or c)
begin
if (a == b)
q <= data;
stop <= 1’b1;
end
else if (a > b)
q <= a;
else
q <= b;
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49. Conditional (if … else) Statement (continued)
Must be careful to define outcome for all possible conditions – failure do do so can cause unintentional inference of latches!
else is paired with nearest if when ambiguous - use begin and end in nesting to clarify.
Nested if … else will generate a “serial” or priority like circuit in synthesis which may have a very long delay - better to use case statements to get “parallel” circuit.
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50. Behavioral Timing Model
How does the behavioral model advance time?
# — delaying a specific amount of time
@ — delaying until an event occurs (“posedge”, “negedge”, or any change)
this is edge-sensitive behavior
wait — delaying until an event occurs (“wait (f == 0)”)
this is level sensitive behavior
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51. What are behavioral models sensitive to?
Quick example
Gate A changes its output, gates B and C are evaluated to see if their outputs will change.
The behavioral model will only execute if it was waiting for a change on the A input
begin
H = ~A;
end
Behavioral model A B
This would execute C …
clock)
Q <= A; A
This wouldn't. Why? H
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52. Order of Execution In what order do these models execute?
Assume A changes. Is B, C, or the behavioral model executed first?
Answer: the order is defined to be arbitrary
All events that are to occur at a certain time will execute in an arbitrary order.
The simulator will try to make them look like they all occur at the same time — but we know better.
Behavioral model A B C
begin
………..
end
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53. Blocking procedural assignments and #
We’ve seen blocking assignments — they use =
Options for specifying delay
#10 a = b + c;
a = #10 b + c;
The details of differences can be seen later.
Note the action of the second one:
an intra-assignment time delay
execution of the always statement is blocked (suspended) in the middle of the assignment for 10 time units.
how is this done?
The difference?
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54. Events — @something always @(posedge ck) q <= d;
Action
when first encountered, sample the expression
wait for expression to change in the indicated fashion
This always blocks
Examples
ck)
q <= d;
or goodbye)
a = b;
always begin
Y= x;
@(posedge hello or negedge goodbye)
a = b; …
end
a = b;
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55. Synthesis from Verilog
Note use of reg in behavioral descriptions; does not always imply actual storage such as latches or registers in synthesis results.
Procedural statements are executed sequentially.
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56. Simulation Time Scales
Compiler Directive `timescale <time_unit> / <time_precision>
time_unit - the time multiplier for time values
time_precision - minimum step size during simulation - determines rounding of numerical values
Allowed unit/precision values:
{1| 10 | 100, s | ms | us | ns | ps}
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57. Simulation Time Scales (continued)
Example:
`timescale 10ps / 1ps
nor #3.57 (z, x1, x2);
nor delay used = 3.57 x 10 ps = 35.7 ps => 36 ps
Different timescales can be used for different sequences of modules
The smallest time precision determines the precision of the simulation.
Will ignore time issues for system tasks/functions
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58. Now, let us simulate our first combinational block
1-Create a project in Quartus that includes these two files.
module Inv (output F; input X);
assign F=~ X; //F is not X
endmodule
===Save to inv.v
module TestBench;
reg X_TB; wire F_TB;
Inv TB (F_TB, X_TB);
initial
begin
X_TB=0;
#10 X_TB=1;
#10 X_TB=0;
#20 X_TB=1;
#15 X_TB=0;
end
===save to TestBench.v
2-Configure Modelsim-Altera to simulate it.
Use Assignments\Settings then select Simulation. Select the option Compile test bench: and click the button Test Benches…. See snapshot
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59. Snapshots of Quartus
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60. Snapshots of Quartus
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61. Snapshots of Quartus
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62. Call Tools\Run Simulation Tool\RTL Simulation
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63. More details
Extra. Read on your own, if interested.
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64. Procedural Continuous Assignment - Examples
// Q is a reg. What does this describe?
(clk)
if clk = 1 assign Q = D;
else assign Q = Q;
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65. Blocking Assignments Identified by =
Sequence of blocking assignments executes sequentially
Example:
clk)
begin
a =2; b = 0; c = 0;
b = a + a;//i.e. 4
c = b + a; //i.e. 6
d = c + a;//i.e. 8
end
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66. Non-Blocking Assignments
Identified by <=
Sequence of non-blocking assignments executes concurrently
Example 1:
assign a=2; //constant
clk)
begin
b <= 0; c <= 0;//not needed
b <= a + a; //4
c <= b + a; //2
d <= c + a;//2
end
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67. Blocking Assignments - Inter-Assignment Delay
Delays evaluation of RHS and assignment to LHS
Example:
wire a; //an input from another block
clk)
begin
b = 0; c = 0;
b = a + a; // uses a at posedge clock
#5 c = b + a; // uses a at posedge clock + 5
d = c + a; // uses a at posedge clock + 5
end /*c = 2 a(at posedge clock)+ a(at posedge clock + 5)
d = 2 a(at posedge clock) + 2 a(at posedge clock + 5)*/
9/18/2018

68. Blocking Assignment - Intra-Assignment Delay
Delays assignment to LHS, not evaluation of RHS
Example:
wire a; //an input from another block
clk)
begin
b = 0; c = 0;
b = a + a; // uses a at posedge clock
c = #5 b + a; // uses a at posedge clock
d = c + a; // uses a at posedge clock + 5
end /* c = 3 a(at posedge clock)
d = 3a (at posedge clock)+ a (at posedge clock + 5)*/
9/18/2018

69. Non-Blocking Assignment - Inter-Assignment Delay
Delays evaluation of RHS and assignment to LHS
Delays subsequent statements
Example:
clk)
begin
b <= 0; c <= 0;
b <= a + a; // uses a at posedge clock
#5 c <= b + a; // uses b and a at posedge clock + 5
d <= c + a; // uses a at posedge clock + 5
end
/*c = b(at posedge clock + 5) + a(at posedge clock + 5)
d = c(at posedge clock + 5) + a (at posedge clock +5) */
9/18/2018

70. Non-Blocking Assignment - Intra-Assignment Delay
Delays only assignment to LHS
Example:
clk)
begin
b <= 0; c <= 0;
b <= a + a; // uses a at posedge clock
c <= #5 b + a; // uses a and b at posedge clock d <= c + a; // uses a and c at posedge clock
end
/* Calculates
c(posedge clock + 5) = b(at posedge clock)+ a(at posedge clock)
d(posedge clock) = c(at posedge clock) + a (at posedge clock) */
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71. Mixed Blocking/Non-Blocking Assignments
Example 1:
clk)
begin
b = 0; c = 0; d = 0;
b = a + a;
c <= b + a + d;
d = c + a;
end
/*Calculates b = 2a, c = 2a, d = a since 1) RHS of c evaluates when statement reached, but LHS assigned to c last after all blocking assignments including that for d and 2) assignment of c does not delay execution of evaluation of d */
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72. Mixed Blocking/Nonblocking Assignments
Example: clk)
begin
d <= 0;//useless. Only last is used
b = a + a;
c = b + a;
d <= c + a;
c = d + a;
end
/* Even though the d <= c + a is non-blocking,
the last assignment c = d + a proceeds to execute after the assignment of d <= c + a.
The resulting values calculated are b = 2a, d = 4a, and c = a + d (value of d is that at posedge clk, not that due to non-blocking assignment statement. */
9/18/2018

73. Mixed Blocking/Nonblocking Assignment
A given register can have either blocking or non-blocking assignments, not both.
Delays cannot be used in always statements with mixed assignments
It is advisable to avoid the confusion of the prior example to write code with all non-blocking assignments last among the code statements
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