1. Geneve The Alps Where is CERN? Jura Mountains Lake Geneva 18-Sep-18
Drew Baden

2. 18-Sep-18
Drew Baden

3. Angels and Demons? CERN’s very own X-33 space plane! 18-Sep-18
Drew Baden

4. LHC 27km proton-proton ring at CERN
Reuse the tunnel previously home for the LEP collider
Dig new collision areas for new experiments
ATLAS & CMS
All high pT physics, hermetic, large, general purpose
LHCb & Alice
Smaller in size and physics scope
18-Sep-18
Drew Baden

5. LHC Layout 8 arcs + 8 straight sections
CMS
LHCb
Atlas
Alice
Betatron “cleaning”
RF & beam instrumentation
Beam dump
Momentum “cleaning”
8 arcs + 8 straight sections
4 intersections have experiments
CMS, Atlas, Alice, LHCb
4 have instrumentation, beam dump, beam focusing, etc
Injection
18-Sep-18
Drew Baden

6. LHC/LEP Tunnel 27km long bored deep underground tunnel Diameter 4 - 6m
Boring is more stable than cut/fill or blasted tunnels
3km are actually under the Jura mountains
Diameter 4 - 6m
Depth m depending on location
1.4 x 106 m3 ~ (100m)3 soil extracted to dig it
18-Sep-18
Drew Baden

7. LHC (cont)
18-Sep-18
Drew Baden

8. …Installation in progress…
LHC Progress
…27 km of dipoles…whew!
…Installation in progress…
18-Sep-18
Drew Baden

9. LHC Stats Ebeam = 7 TeV, 2 counter-circulating proton beams
Bunched beam structure
Crossing every 25ns
Number of bunches 3654
1.1x1011 particles/bunch
DC beam current .56Amps
Stored beam energy 350 MJoules
Equivalent to ~100 kW-hrs Superconducting NbTi 1.9K
Dipole field 7 TeV full beam energy
18-Sep-18
Drew Baden

10. CMS (cont)
18-Sep-18
Drew Baden

11. TriDAS Overview CMS HCAL Trigger/DAQ
CMS Trigger: Emphasis is on bandwidth and commercial processors
Level 1
3 ms latency inside L1 trigger
100 kHz average L1 accept rate (1/400)
100 Gbyte/sec into Level 2
Level 1
Trigger
HCAL Data
QIE
Fibers
Trigger/DAQ
Level 2/3
DAQ
CMS HCAL
“Front End”
Baden is HCAL “Level 3 WBS Manager” for TriDAS
18-Sep-18
Drew Baden

12. HCAL Electronics Overview
FE MODULE
FRONT-END
Readout Box
(RBX)
On detector
HPD
Shield
Wall
SBS
12 HTRs
READ-OUT Crate
Trigger Primitives
GOL
TTC H T R
Level 1
TRIGGER
CERN Transmitter
40 bits
@40 MHz
20 bits
@ 80 MHz
=1.6 Gbps
FIBERS
S-Link: MHz
Rack CPU
CLK
QIE
CCA
2 DCC
1 PC Interface
1 Clk board D C
analog optical
signals from
HCAL
18-Sep-18
Drew Baden

13. HTR Principal Functions
Receive HCAL data from front-ends
Synchronize optical links
Data validation and linearization
Form “trigger primitives” and transmit to Level 1 at 40 MHz
Pipeline data, wait for Level 1 accept
Upon receiving L1A:
Zero suppress, format, & transmit raw data to the concentrator (no filtering)
Transmit all trigger primitives along with raw data
Handle DAQ synchronization issues (if any)
Calibration processing and buffering of:
Radioactive source calibration data
Laser/LED calibration data
Support a VME data spy monitoring
Data: total of approximately 650 TB/sec flowing through our boards!!!
18-Sep-18
Drew Baden

14. HCAL Trigger/Readout (HTR) Board
Princeton
Fanout Card
(1/VME crate)
Fiber Data
Serial Optical Data LC
Deserializers (8)
CLK80
Ref Clk
Recovered Clk 20
TTC
TTCrx
Crystal
RX_BC0
RX_CLK40
PLL
TTC 40 Clk x2
SLB
All I/O on front panel
Fiber digital data
Copper output to L1 and DCC
FPGA logic
Fully programmable
SYS80 Clk
Async Fifo
SLB
TTC Broadcast
SLB
SYS40 Clk
TPG Path
SLB
XILINX
SLB
SLB
18-Sep-18
Drew Baden

15. HTR Card Production Version (Rev 4)
Dual-LC O-to-E
VME
Stiffeners
TTC mezzanine
Deserializers
6 SLBs
Xilinx XC2V3000-4
18-Sep-18
Drew Baden

16. Firmware DAQ format evolving Top-level view:
Maryland/Boston/Princeton collaboration
Top-level view:
See
18-Sep-18
Drew Baden

17. LHC Clocking LEP ring is sensitive to:
Distortions in the large (27 km) circumference
Tidal distortions
Pressure from Lake Geneva
Return currents from DC trains running nearby
LHC RF clock keeps 3564 buckets of protons circulating
CMS must remain synchronous with this clock
LEP was concerned about DE~few MeV, LHC will be concerned with Df ~ 25 ppm
We have learned to handle this…
Train to Bellgarde EFFECT
LAKE Geneva EFFECTS
TIDAL EFFECTS
18-Sep-18
Drew Baden

18. Timing Signal Distribution
Trigger Timing Control
TTC Stream (“RX_CLK”) F A N O U T F A N O U T F A N O U T
Rack-to-Rack CAT 7
ECAL H T R H T R H T R H T R D C F A N O U T H T R H T R H T R H T R D C F A N O U T
HCAL VME Crates
Timing is critical in a synchronous pipeline experiment!
18-Sep-18
Drew Baden

19. Fanout board 2 operating modes: Global or Crate
TTCrx
TTC fiber
TTC Broadcast
40MHz
QPLL can run stand-alone G
Clk80 G C
QPLL
18 Outputs G C
RX_CLK = 40MHz G
INT_BC0
FPGA
RX_BC0 C
EXT_BC0
Delay
RX_CLK = 40MHz
Input from GLOBAL Fanout
RX_BC0
EXT 80MHz
18-Sep-18
Drew Baden

20. Overall TriDAS Project Cost
Contingency:
Effort: 50%
M&S: 75%
Based on the uncertainty in the requirements, which will certainly change over time.
Item
Cost
Effort:
Engineering
$802,669
Technician
$138,684
Total
$941,353
M&S:
R&D
$ 218,100
Production
$1,929,374
$2,147,474
Misc:
$45,000
Grand Total
$3,133,827
18-Sep-18
Drew Baden