1. Wireless Sensor Network
A Second-Generation Sensor Network Processor with Application-Driven Memory Optimizations and Out-of-Order Execution* by
Banit Agrawal
*Paper published in CASES 2005 by U Michigan Group
9/18/2018
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2. Outline Introduction Applications of wireless sensor networks
Wireless Sensor Network (WSN) Architecture
WSN’s Microprocessor
UMich first generation processor
UMich second generation processor
Conclusion
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3. What is wireless sensor network
Wireless Sensor Network (WSN)
Network of many small distributed computers for processing the sensor data
Usually consists of microprocessor, memory, transceiver, sensing device, battery/energy scavenging unit, etc
Resource constrained
Everything optimized for low-energy operations
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4. Current Challenges Energy Conservation Limited Computation/Storage
Scalability
Fault-tolerance
Routing/Communication
Bandwidth
Autonomous and Distributed Systems
Security
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5. Applications (1) Health monitoring Environmental Monitoring
Habitat Monitoring
Integrated Biology
Structural Monitoring
Building/Border/Battlefield detection
Road/traffic monitoring
Health monitoring
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6. Applications (2) Context-aware computing Automation
Business Applications
Supply Chain Management
Expired/Damaged Goods Tracking
Automatic Checkout Systems
Security, surveillance
Context-aware computing
Automation
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7. WSN Node Architecture Ref: Energy-Aware Wireless Microsensor Networks
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8. Berkeley Motes
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9. Sensoria SGATE hardware
Processor
RAM
Flash
GPS
Address/Data Bus
DSP
Preprocessor
Multi-
Channel
Sensor
Interface
Analog
Front
End
Imager
Module
Modular
Wireless and Digital Interfaces RF
Modem 1 2
Digital
I/O
10/100
Ethernet
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10. UCLA Sensor Nodes
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11. MIT AMPS
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12. Intel StarGate
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13. Harvard’s University (ISCA’05)
Micro
Controller
Event Processor
System Bus
Interrupt
Power Ctrl
Addr/Data
SRAM
Sensors
Radio
Message Processor
Data Filter
Timer
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14. Berkeley’s Experimental Platform
Telos 4/04
Robust
Low Power
250kbps
Easy to use
Services
Networking
TinyOS
Small microcontroller kB code B data
Simple, low-power radio kbps ASK
EEPROM (32 KB)
Simple sensors
WeC 99
“Smart Rock”
Rene 11/00
Designed for experimentation
sensor boards
power boards
Mica 1/02
NEST open exp. Platform 128 kB code, 4 kB data 40kbps OOK/ASK radio 512 kB Flash
Dot 9/01
Demonstrate scale
Mica2 12/02
38.4kbps radio FSK
Spec 6/03
“Mote on a chip”
Ref: HotChips 2004 – “Mote Evolution…”
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15. Mote Evolution Ref: HotChips 2004 – “Mote Evolution…” 9/18/2018
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16. WSN’s Microcontroller
AT/ATmega/ATMEL (AVR) Family
TI Family
Intel XScale
StrongARM
Harvard’s microcontroller
UMich’s first generation processor
UMich’s second generation processor
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17. Processor Requirements
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18. Not Performance, Energy is important.
Voltage Reduction
Not Performance, Energy is important.
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19. Sensor Network Applications
Representative set to evaluate architecture
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20. Optimizing Energy Efficiency
Reduce the area to minimize the static power
Transistor utility must be maximized
CPI must be minimized
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21. Processor’s Characteristics
12-bit RISC ISA
8-bit datapaths
Flexible Operand Handling
Application specific instructions
Prefetch mechanism
Memory Architecture
Branch speculation and out-of-order execution
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22. ISA: RISC Encoding 12-bit RISC encoding simple decoding logic
Reducing code-density and hence area to reduce the leakage energy
96.2% encoding efficiency
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23. ISA Organization
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24. ISA Design Load-store architecture Simple to design and pipeline
8 registers
Simple to design and pipeline
2-operand based design
Preserve bit to save the source
Various addressing modes available
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25. ISA Design (2) Micro-operations Application specific instructions
Efficient pointer and carry manipulation
Event scheduler control
Timer control
Reduction in code-size
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26. Data memory predecode architecture [May not be useful for pointers]
Memory Optimizations
Data memory predecode architecture [May not be useful for pointers]
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27. Memory Optimizations (2)
Instruction memory predecode architecture
2 words and automatically increment the page when PC reaches the end of page
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28. Processor pipeline design
3-stage pipeline [optimum, not 4 not 2]
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29. Microarchitectural Optimizations
Out-of-order execution
Taken branch speculation
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30. Results
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31. Results: Contributions
Storage unit and other components
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32. Related Works 8-bit ATmega - 1.5 nJ/instruction
Clever Dust 2 – 12 pJ/instruction
StrongARM/XScale - 1nJ/instruction
SNAP/LE – 24 pJ/instruction
Umich first generation – 1.6 pJ/instruction
Umich second generation – 600fJ/instruction
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33. Conclusion
Energy-efficient processor (600 fJ/instruction, will run 312 years on single AAA)
Microarchitectural and ISA optimizations to reduce the leakage energy
IBM 130nm fabrication
Intra-ocular pressure sensor
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34. Thanks for your attention.
Questions ?
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