Algorithms for VLSI Design Automation

Algorithms for VLSI Design Automation
Instructor D. Zhou Phone: Office: ECN 4.610 The 1st lecture

Dragon Star Shot Course
Outline History and the road map Traditional design flow Physical design fundamentals Performance issues System on chip The 1st lecture 2018/9/18 Dragon Star Shot Course

History and the road map
The history of IC The invention of transistor The invention of integrated circuit IC has changed our life Moore’s Law IC performance and complexity have been doubled in every two years Road Map Insert a picture for Moles Law Insert a picture for road map The NSF funding traind 2018/9/18 Dragon Star Shot Course

The invention of transistor
John Bardeen, Walter Brattain & Wiliam Shockley in vented “The first transistor” in 1947. 2018/9/18 Dragon Star Shot Course

The invention of integrated circuit
Jack Kilby & Robert Noyce inveted “The Integrated Circuit” in 1958. 2018/9/18 Dragon Star Shot Course

Moore’s Law In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 14 months (i.e., grow exponentially with time). Amazingly visionary – million transistor/chip barrier was crossed in the 1980’s. 2300 transistors, 1 MHz clock (Intel 4004) 16 Million transistors (Ultra Sparc III) 42 Million, 2 GHz clock (Intel P4) 140 Million transistor (HP PA-8500)

Intel 4004 Microprocessor introduced in versus introduced in 1978 1 MHz clock rate MHz clock rate 5volt VDD (?) volt VDD 10 micron (?) micron 5K transistors (?) K transistors

Intel Pentium (IV) Microprocessor
P5 introduced in versus P6 (Pentium Pro) in 1996 75 to 100 MHz clock rate to 200 MHz clock rate 91 mm** mm**2 3.3M transistors M transistors (1M in cache) (external cache) 0.35 micron micron 4 layers metal layers metal 3.3volt VDD volt VDD >20W typical power dissipation 387 pins

Moore’s Law in Microprocessors
Transistors on lead microprocessors double every 2 years 4004 8008 8080 8085 8086 286 386 486 Pentium® proc P6 0.001 0.01 0.1 1 10 100 1000 1970 1980 1990 2000 2010 Year Transistors (MT) 2X growth in 1.96 years! Courtesy, Intel

Evolution in DRAM Chip Capacity
human memory human DNA 4X growth every 3 years! 0.07 m 0.1 m 0.13 m encyclopedia 2 hrs CD audio 30 sec HDTV book m m m m m m page

Die size grows by 14% to satisfy Moore’s Law
Die Size Growth Die size grows by 14% to satisfy Moore’s Law 4004 8008 8080 8085 8086 286 386 486 Pentium ® proc P6 1 10 100 1970 1980 1990 2000 2010 Year Die size (mm) ~7% growth per year ~2X growth in 10 years Courtesy, Intel

Lead microprocessors frequency doubles every 2 years
Clock Frequency Lead microprocessors frequency doubles every 2 years 10000 2X every 2 years 1000 P6 100 Pentium ® proc 486 Frequency (Mhz) 10 386 8085 286 8086 Causes: shrinking feature size and increased pipelining 8080 1 8008 4004 0.1 1970 1980 1990 2000 2010 Year Courtesy, Intel

Power Dissipation Lead Microprocessors power continues to increase
100 P6 Pentium ® proc 10 486 286 Power (Watts) 8086 386 8085 1 8080 8008 4004 0.1 1971 1974 1978 1985 1992 2000 Year Power delivery and dissipation will be prohibitive Courtesy, Intel

Power density too high to keep junctions at low temp
4004 8008 8080 8085 8086 286 386 486 Pentium® proc P6 1 10 100 1000 10000 1970 1980 1990 2000 2010 Year Power Density (W/cm2) Rocket Nozzle Nuclear Reactor Hot Plate Power density too high to keep junctions at low temp Courtesy, Intel

International Technology Roadmap for Semiconductors (ITRS)
Technology Trend International Technology Roadmap for Semiconductors (ITRS) Production year 2002 2003 2004 2005 2006 2007 MPU Gate length (nm) 75 65 53 45 40 35 Clock (GHz) 2.3 3.1 4.0 5.2 5.6 6.7 Metal layers 8 9 Supply voltage (V) 1.0 0.9 0.7

Traditional design flow
Traditional design flow (see slides design-flow) What has not been addressed in depth Understand application Architecture synthesis Verification is not complete 2018/9/18 Dragon Star Shot Course

2018/9/18 Dragon Star Shot Course

Performance issues Speed Noise Clock distribution Power distribution Low power 2018/9/18 Dragon Star Shot Course

SOC A low cost solution Challenges Modeling Simulation Mixed signal Different processing Timing 2018/9/18 Dragon Star Shot Course

Agenda Dealing with technology Masks Front-end manufacturing Back-end manufacturing Application requirements Putting it all together 2018/9/18 Dragon Star Shot Course

Semiconductor Process Flow
Design EDA $3.6B Masks $2.8B Mask Data Systems $1050B Manufacturing $2.3B Tools $0.5B Computers Communications Consumer Industrial, Military… EDA $2.7B Comp Platforms Masks Front-End Manufacturing $24B Embedded SW $0.8B Process Auto $1B Lithography $6B Etch/Doping $6B Diffusion $1B Deposition $5B Other (CMP, Ion, Photoresist, etc.) $5B IP $0.9B Semiconductors $119B Micros, DSP $45B Memory $25B ASIC, ASSP $25B Analog, Discrete $25B Wafer $4B Back-End Manufacturing $6B Bonding $1B Packaging $2B Test equipment $3B Chips 2018/9/18 Dragon Star Shot Course Market size for Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates

Exploding Mask Costs Year 1999 2002 2004 2007 Node .18µm .13µm .9µm .065µm Cost $ K $500K-1M $800K-1.2M $1-2M 256GB 1024GB 64GB 16GB Data Raster scan patterning exposure time for a 110mm x 110 mm mask is 6.5 hrs and 20 hrs with fine granularities (60nm vs. 120nm pixel size) Largest cost contribution to mask making is mask exposure time (capital cost ~$20M) RET is being absorbed by CAD vendors into layout verification / tape-out suites. RET may move up into routing, placement 2018/9/18 Dragon Star Shot Course Source: Thomas Weisel Partners

Front-End Processing EDA $3.6B Masks $2.8B Systems $1050B Design Mask Data Manufacturing $2.3B Tools $0.5B Computers Communications Consumer Industrial, Military… EDA $2.7B Comp Platforms Masks Front-End Manufacturing $24B Embedded SW $0.8B Process Auto $1B Lithography $6B Etch/Doping $6B Diffusion $1B Deposition $5B Other (CMP, Ion, Photoresist, etc.) $5B IP $0.9B Semiconductors $119B Micros, DSP $45B Memory $25B ASIC, ASSP $25B Analog, Discrete $25B Wafer $4B Back-End Manufacturing $6B Bonding $1B Packaging $2B Test equipment $3B Chips Market size for Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates 2018/9/18 Dragon Star Shot Course

Interconnect Exploding number of metal layers, mask cost Large number of vias diminishes yield Increasingly complex process rules Via Stack Multiple Array Metal Min, max, spacing, width Antenna Signal EM Number of vias for a given load, frequency Include pattern density & shape management in layout, extraction Limit vias / multiple vias Include pattern density/shape management in layout, extraction Limit vias / multiple vias 2018/9/18 Dragon Star Shot Course

CD Variation Across a Wafer Wafer Map for No-DPC Horizontal Isolated Structures 2.3 2.2 2.1 2.0 1.9 1.8 50 100 150 20 40 60 LineWidth [nm] x 10-7 Wafer Y Incorporate analysis of timing variation into extraction & static timing analysis 2018/9/18 Dragon Star Shot Course Source: Spanos, UCB

Physical design for Yield / Reliability
Aggressive via minimization in routing Insert redundant vias Space / Width Limit Current Density 2018/9/18 Dragon Star Shot Course

Back-End: Assembly and Packaging
EDA $3.6B Masks $2.8B Systems $1050B Design Mask Data Manufacturing $2.3B Tools $0.5B Computers Communications Consumer Industrial, Military… EDA $2.7B Comp Platforms Masks Front-End Manufacturing $24B Embedded SW $0.8B Process Auto $1B Lithography $6B Etch/Doping $6B Diffusion $1B Deposition $5B Other (CMP, Ion, Photoresist, etc.) $5B IP $0.9B Semiconductors $119B Micros, DSP $45B Memory $25B ASIC, ASSP $25B Analog, Discrete $25B Wafer $4B Back-End Manufacturing $6B Bonding $1B Packaging $2B Test equipment $3B Chips Market size for Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates 2018/9/18 Dragon Star Shot Course

Assembly and Packaging
The chip is assembled into a package that provides the contact leads for the chip. A wire-bonding machine attaches wires to the leads of the package; or this is achieved using flip chip die attach. Modern packages can be very complex The package is the bridge between silicon and system Differentiator: Performance, form factor, fit, thermal conduction, reliability, and cost 2018/9/18 Dragon Star Shot Course

IC / Package Co-Design for Flip Chip
Lid Chip Package Pwr, Gnd Signal Solder balls Board Design Package feasibility Bump patterning, assignment P/G assignment Driver placement Routing Analyis Extraction RLC Simulation Spice The chip is assembled into a package that provides the contact leads for the chip. A wire-bonding machine attaches wires to the leads of the package; or this is achieved using flip chip die attach. Modern packages can be very complex The package is the bridge between silicon and system Differentiator: Performance, form factor, fit, thermal conduction, reliability, and cost Trends by 2005 Cost: 0.29¢ to 2.28¢ / pin Pins / package: 120 – 3000 Performance: 600 MHz – 2GHz Integrating complete (sub)systems on a chip is often driven by packaging Less I/O, power, area, & cost Higher on-chip speed, reliability Multi-chip modules that require routing and analysis, driven by mixed-signal, RF, memory integration 2018/9/18 Dragon Star Shot Course

SoC Packaging Trends by 2005 Cost: 0.29¢ to 2.28¢ / pin Pins / package: 120 – 3000 Performance: 600 MHz – 2GHz Integrating complete (sub)systems on a chip is often driven by packaging Less I/O, power, area, & cost Higher on-chip speed, reliability Complex packages and Multi-chip modules that require routing and analysis, driven by mixed-signal, RF, memory integration 2018/9/18 Dragon Star Shot Course

Back-End: Testing and Automatic Test Equipment

Key Trends By 2005 Cost: $2-5k/pin ( high performance) Pins / package: 1900 Performance: up to 2 GHZ Tester timing accuracy growing at 12% per year ASIC speeds growing at 30% per year IDDQ becoming less meaningful For every 80mV of VT decrease Ioff increases 10x!! Higher leakage currents make IDDQ values increase dramatically as transistor density increases More mixed-signal testing 2018/9/18 Dragon Star Shot Course

Application Requirements

Heterogeneity - SoC Analog RF Power MEMs IP Digital Control µP DSP Interfaces Memory SRAM DRAM FLASH 2018/9/18 Dragon Star Shot Course

What EDA Must Provide… System level design Soc design&test, verification methodology Need hierarchy in the design flow Analog, digital, RF, MEMs IP for soc construction / verification: processors, memory, peripherals, etc. Soc design for debug (debug busses and controllers) 2018/9/18 Dragon Star Shot Course

ASIC, ASSP, ASIP, GA, FPGA ASIC & ASSP differ only by how they are sold and used, not by how they are designed Early market characteristics  ASICs Late market characteristics  ASSPs Trend toward application-specific instruction processors Many processors on a chip Metal Programmability (GA) gaining attention again SW Programmable (FPGA), reconfigurable parts gaining importance Embedded FPGA / GA 2018/9/18 Dragon Star Shot Course

Power 1400 Dynamic power density 1200 1000 800 mW/mm2 600 400 Leakage power density 200 Power scaling (Vt for high performance, constant function, switched C from 600 pF/mm2 to 2000pF/mm2) 0.18 µm 0.13 µm 0.10 µm 0.05 µm 2018/9/18 Dragon Star Shot Course

Solutions for Low Power Design
Power modeling and analysis Clock gating and clock tree optimization Variable Vdd Power gating Multi - Vdd Dynamic voltage scaling Leakage optimization using multi-Vt Modelling process variation Support Asynchronous design 2018/9/18 Dragon Star Shot Course

Dual Vt 180nm 130nm Leakage power [ ] nW Leakage power [ ] nW Cell number [0-467] Cell number [0-519] typical version 2018/9/18 Dragon Star Shot Course From Ali Dasdan

Speed Determined by interconnect The primary physical effect of concern is cross-coupled capacitance plus the Miller effect. This may cause: functional errors in analog circuitry or dynamic logic timing errors in static digital circuitry IR Drop (static leakage and dynamic IR drop) handled in power Other important effects & features are Inductance, CD variation, EM V dd R ss I IR D V = - 2018/9/18 Dragon Star Shot Course

Putting it All Together: EDA

SoC Design Synthesis Design Services Architecture Design
Test Power Physical Synthesis IP Architecture Design Design Planning Design Database Verification IP Assertions and Testbenches Languages Timing and Signal Integrity Physical Implementation Smart Verification Extraction Physical Verification Mixed Signal / Analog Mask Synthesis / OPC 2018/9/18 Dragon Star Shot Course

Implementation Nodes 2018/9/18 Dragon Star Shot Course

Functional Verification
Driven by complexity Verification models (IP) Avenues of development Higher levels Performance Integration New (formal) technologies Emulation competes with Prototyping (enabled by multi-million gate FPGAs) Compute farms (Linux) Assertions and Testbenches Languages Smart Verification Architecture Design Mixed Signal / Analog Verification IP 2018/9/18 Dragon Star Shot Course

Functional Verification 2003
Standard based IP, Star IP on AMBA (System) Verilog for HW SystemC for system level design (SW) Languages for testbenches, assertions being standardized Integrated simulation (System)Verilog/VHDL Fast Spice/Spice Testbenches Language Assertions (monitor) Constraint solver Formal verification Equivalence checking Semi-Formal property checking Assertions and Testbenches Languages Smart Verification Architecture Design Mixed Signal / Analog Verification IP 2018/9/18 Dragon Star Shot Course

Summary Dealing with technology Masks RET, OPC, PSM Front-end manufacturing Interconnect, CD variation, dishing, DFM Back-end manufacturing Packaging, test Application requirements Heterogeneity, cost, power, speed Putting it all together Implementation flow, verification flow However, It is not without challenge to adopt a design reuse approach. For those of you who said that you’ve used 3rd party IP, you may have been familiar with these problems already. In the 3rd part IP market, many users were frustrated by the high cost, complex business model, horrors of legal process and contract negotiation, support struggles and poor qualities. 2018/9/18 Dragon Star Shot Course

Algorithms for VLSI Design Automation

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