1. RTL Design Methodology
Lecture 9
RTL Design Methodology

2. Structure of a Typical Digital System
Data Inputs
Control & Status Inputs
Control
Signals
Datapath
(Execution
Unit)
Controller
(Control
Unit)
Status
Signals
Data Outputs
Control & Status Outputs

3. Hardware Design with RTL VHDL
Interface
Pseudocode
Datapath
Controller
Block
diagram
Block
diagram
State diagram
or ASM chart
VHDL code
VHDL code
VHDL code

4. Steps of the Design Process
Text description
Interface
Pseudocode
Block diagram of the Datapath
Interface with the division into the Datapath
and the Controller
ASM chart of the Controller
RTL VHDL code of the Datapath, the Controller, and the Top Unit
Testbench of the Datapath, the Controller, and the Top Unit
Functional simulation and debugging
Synthesis and post-synthesis simulation
Implementation and timing simulation
Experimental testing

5. Steps of the Design Process Practiced in Class Today
Text description
Interface
Pseudocode
Block diagram of the Datapath
Interface with the division into the Datapath
and the Controller
ASM chart of the Controller
RTL VHDL code of the Datapath, the Controller, and the Top Unit
Testbench of the Datapath, the Controller, and the Top Unit
Functional simulation and debugging
Synthesis and post-synthesis simulation
Implementation and timing simulation
Experimental testing

6. min_max_average
example

7. Circuit Interface clk DONE reset n n in_data out_data 5 MIN_MAX_AVR
in_addr 2
out_addr
write
START

8. Interface Table Port Width Meaning clk 1 System clock reset
System reset – clears internal registers
in_data n
Input data bus
in_addr 5
Address of the internal memory where input data is stored
write
Synchronous write control signal
START
Starts the computations
DONE
Asserted when all results are ready
out_data
Output data bus used to read results
out_addr 2
01 – reading minimum
10 – reading maximum
11 – reading average

9. Pseudocode [load input data] [load input data] Max = 0 Min = 2n-1
FOR m=5
FOR any m
[load input data]
[load input data]
Max = 0
Min = 2n-1
Sum = 0
for i=0 to 31 do
Max = 0
Min = 2n-1
Sum = 0
for i=0 to 2m-1 do
Sum = Sum + Mi
if (Mi > Min) then
Min = Mi
endif
if (Mi < Max) then
Max = Mi
Sum = Sum + Mi
if (Mi > Min) then
Min = Mi
endif
if (Mi < Max) then
Max = Mi
endfor
endfor
Sum = Sum >> 5
Sum = Sum >> m
[read output data]
[read output data]

10. sorting
example

11. Sorting - Required Interface
Clock
Resetn
DataIn N
DataOut
Done
RAdd L
WrInit S
(0=initialization
1=computations) Rd

12. Sorting - Required Interface

13. Simulation results for the sort operation (1) Loading memory and starting sorting

14. Simulation results for the sort operation (2) Completing sorting and reading out memory

15. Sorting - Example During Sorting 1 2 3 3 3 2 2 1 1 1 1 2 2 3 3 3 3 2 2
After
sorting
Before
sorting
i=0 i=0 i=0 i=1 i=1 i=2
j=1 j=2 j=3 j=2 j=3 j=3
Address 1 2 3
Legend:
position of memory
indexed by i
position of memory
indexed by j Mi Mj

16. Pseudocode [load input data] [load input data] for i = to 2 do for i =
FOR k = 4
FOR any k ≥ 2
[load input data]
[load input data]
for i = to 2 do
for i = to k 2 do A M ; j + 1 B if
<
then
endif
endfor; – A = M ; i
for j = i + 1 to 3 do B = M ; j if B
< A
then M = B ; i M = A ; j A = M ; i
endif ;
endfor;
endfor;
[read output data]
[read output data]

17. Pseudocode wait for s=1 for i=0 to k-2 do A = Mi for j=i+1 to k-1 do
B = Mj
if A > B then
Mi = B
Mj = A
end if
end for
Done
wait for s=0
go to the beginning

18. Block diagram of the Execution Unit
DIN
DOUT
ADDR WE
CLK EN
RST
A>B 1
WrInit
Clock
Resetn Wr
Bout EA EB
AgtB
Addr
Int
DataIn
RAdd
Rdout
DataOut
Csel LD Li Ei Lj Ej
= k-2
= k-1 zi zj N L
ABMux A B i j
Mij
Din We +1
Block diagram of the Execution Unit

19. Interface with the division into the Datapath and the Controller
DataIn
RAddr
WrInit
Clock
Resetn s Rd N L
AgtB zi
Int Wr Li Ei Lj Ej EA EB
Bout
Csel
Rdout zj
Datapath
Controller N
DataOut
Done

20. Project
SHA-3 Core Interface

21. w
SHA core
din
dout
src_ready
src_read
dst_ready
dst_write
clk
rst

22. SHA core Input Output FIFO fifoin_empty fifoin_read idata w odata
fifoout_full
fifoout_write
fifoin_full
fifoin_write
fifoout_empty
fifoout_read
Input
FIFO
SHA core
clk
rst
ext_idata
ext_odata
din
dout
src_ready
src_read
dst_ready
dst_write
full
empty
write
read
Output

23. b) a) w bits msg_bitlen seg_0_bitlen seg_0 . message seg_1_bitlen
zero_word
−−−−−
message
w bits .
seg_0_bitlen
seg_0
seg_1_bitlen
seg_1 
seg_n-1_bitlen
seg_n-1 a) b)